Analysis of performance of SiC bipolar semiconductor devices for grid-level converters

Recent commercialization of SiC bipolar devices, including SiC BJT, SiC MPS diode and SiC PiN diodes have enabled potential candidates to replace their SiC unipolar counterparts. However, the prospects of 4H-SiC power bipolar devices still need further investigation. This thesis compares the static and dynamic performance and reliability for the commercial SiC bipolar devices including SiC BJT, SiC MPS diode and SiC PiN diode and their similarly rated Silicon counterparts mainly by means of experimental measurements.Through comprehensive double-pulse measurements, the turn-on and turn-off transition in Silicon BJT is seen to be much slower than that of the SiC BJT while the transient time will increase with temperature and decreases with collector currents. The common-emitter current gain (β) of SiC BJT is also found to be much higher than its Silicon counterpart. Significant turn-off delay is observed in single Si BJT which becomes worse when in parallel connection as it aggravates the current mismatch across the two devices, while this delay is almost non-existent in SiC devices. The current collapse seen in single SiC BJT is mitigated by parallel connection. These are dependant on temperature and base resistance, especially in the case of Silicon BJT. The static performance of power Silicon and SiC BJT has also been evaluated. It has been found that the higher base-emitter junction voltage of SiC BJTs enables quasi-saturation mode of operation with low on-resistance, which is also the case for Silicon BJTs only at high base currents. In terms of DC gain measured under steady state operation, the observed negative temperature coefficient (NTC) of β in SiC BJTs and the positive coefficient (PTC) in Silicon BJTs can make the β of SiC BJT lower than that in Silicon at high temperatures. It has been found that parallel connection promotes both the on-state conductivity and current gain in Silicon BJTs and conductivity in SiC BJTs.The characterization of power diodes reveals that the superior switching performance of the SiC MPS & JBS diode when compared with the Si PiN diode is due to the absence of the stored charge. This also leads to the larger on-state voltage in both SiC diodes and becomes worse at high currents under high temperatures. Through comprehensive Unclamped Inductive Switching (UIS) measurements, it is seen that the avalanche ruggedness of SiC MPS & JBS diodes outperform that of the closely rated Silicon PiN diode taking advantage of the wide-bandgap properties of SiC. Higher critical avalanche energy and thus better avalanche ruggedness can also be observed in SiC JBS diode compared with the SiC MPS diode. SiC MPS diodes can compete with Si PiN diodes in terms of the surge current limits, while the SiC JBS diode failed under a lower electrothermal stress. This is observed by the dramatic increase in its reverse leakage current at lower voltages.The 15 kV SiC PiN diodes feature smaller device dimensions, less reverse recovery charge and less on-resistance when compared to the 15 kV Silicon PiN diodes. Nevertheless, when evaluating its long-term reliability by using the aggravated power cycling configuration, the high junction temperature together with the dislocation defects in the SiC PiN diode accelerate its degradation. Such degradations are not observed in Silicon PiN diodes for the same junction temperature and high-temperature stress periods

Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, performance at 1 st and 3 rd quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 st quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 rd quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery

Development of a fault tolerant MOS field effect power semiconductor switching transistor

This work describes the development of a semiconductor switch to replace an electromechanical contactor as used within the electrical power distribution system of the More Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The MEA is safety critical and therefore requires highest reliability components and systems, but subsequent to a short circuit load fault the electro-mechanical contactor switch often welds shut. This risk is increased when using high discharge energy lithium ion dc batteries. Predominately the semiconductor switch controls inductive loads and is required to safely turn off current of up to 10 times the nominal level during sporadic load fault events. The switch requires the lowest static loss (lowest on state resistance), but also the lowest dynamic loss (losses due to the switching event). Presently, unipolar devices provide the lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which is sized to suit the fault current, but at relatively high cost in terms of silicon area. The resultant area is typically achieved by several die connected in parallel, unfortunately, such a solution suffers from current share imbalance and the potential of cascade die failure. The use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid which proves challenging if the load current is to be shared appropriately during fault switching in order to prevent failure. Some form of single MOS (Metal Oxide Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore required to ensure highest reliability through a non latching design which offers lowest losses under all conditions and achieves an even temperature distribution. In this work the novel concept of the integrated hybrid device has been investigated at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises a novel merged Schottky p-type injector to provide self biased entry into a reduced static loss bipolar state in the event of high fault current. The device achieves a specific on state resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon limit line and requires half the area of a traditional unipolar MOSFET to conduct fault current. During comparative standard unclamped inductive switching trials, the hybrid device provides a self clamping action which enables increased inductive energy switching (higher inductance and/or higher load current), relative to that achieved by either the MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically >10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device is latch up free across the operational temperature range of T=233 K to 400 K. A viable charge balanced structure to increase the BV rating to approximately 600 V is also proposed. The resulting performance of the single gated, self biased, hybrid, utilising a novel merged Schottky/P type injector, could lead to a new class of rugged MOS gated power switching devices in silicon and potentially silicon carbide

Finite element electrothermal modelling and characterization of single and parallel connected power devices

Power modules typically comprise of several power devices connected in parallel for the purpose of delivering high current capability. This is especially the case in SiC where small active area and low current MOSFETs are the only option due to defect density control and yield issues in the epitaxial growth of SiC wafers. Electrothermal variations between parallel connected devices can emerge from manufacturing variability, non-uniform degradation rates, variation in gate driving just to mention a few. The impact of electrothermal variation between parallel-connected devices as a function of device technology is thus important to consider especially since failure of the power module requires only failure in a single device. Furthermore, the impact of these electrothermal variations in parallel-connected devices on the total electrothermal ruggedness of the power module under anomalous switching conditions like unclamped inductive switching is important to consider for the different device technologies. In this thesis, the impact of initial junction temperature variation, switching rates and thermal boundary conditions between parallel-connected diodes have been evaluated for SiC Schottky and silicon PiN diodes under clamped and unclamped inductive switching. Finite element simulations have been used to support the experimental measurements. Similar studies have been performed in CoolMOS super-junction MOSFETs, silicon IGBTs and SiC power MOSFETs. New insights regarding the failure of parallel connected devices under unclamped inductive switching have been revealed from the models and measurements. Overall, the thesis makes a major contribution in the understanding of the electrothermal performance of parallel connected devices for different transistor and diode technologies

A comprehensive study of the short-circuit ruggedness of silicon carbide power MOSFETs

The behavior of Silicon Carbide Power MOSFETs under stressful short circuit conditions is investigated in this paper. Illustration of two different short-circuit failure phenomena for Silicon Carbide Power MOSFETs are thoroughly reported. Experimental evidences and TCAD electro-thermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations, and are reported along with their effects on devices short-circuit capability

Investigation of performance of double-trench SiC Power MOSFETs in forward and reverse quadrant operation

In this paper, dynamic switching performance at 1st quadrant and 3rd quadrant operation of Silicon and Silicon Carbide (SiC) trench, double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements. The devices are evaluated on a high voltage clamped inductive switching test rig and switched with a range of switching rates at elevated junction temperatures. It is shown experimentally that, at 1st quadrant, CoolSiC MOSFET and SiC Double trench MOSFET show good stability in regard to temperature variations. Silicon superjunction MOSFETs perform unacceptably at turn-OFF transient due to their large input capacitance and are unstable with temperature variation due to the more temperature-dependent CGD. SiC Planar MOSFET also performs poorly at turn-ON switching due to its low transconductance and gate threshold voltage variation leading to variations of switching rate with temperature at both turn-ON and turn-OFF transients. At 3rd quadrant, Silicon Superjunction MOSFET causes large switching loss due to its long reverse recovery process, while SiC Double trench MOSFET and CoolSiC MOSFET show stable performance with temperature variation due to the negligible reverse recovery charge