Optimal and robust control for a small-area FLL

International audienceFine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each voltage and frequency island must be taken into account to optimize the circuit. A small-area fast-reprogrammable Frequency-Locked Loop (FLL) engine is a suited option, since its implementation in 32nm represents 0.0016mm 2, being 4 to 20 times smaller than classical techniques used such as a Phase-Locked Loop (PLL) in the same technology. Another relevant aspect with respect to the FLL is the control design, which must be suited for low area hardware. In this paper, an analytical model of the system is deduced from accurate Spice simulations. It also takes into account the delay introduced by the sensor. From this model, an optimal and robust control law with a minimum implementation area is developed. The closed-loop system stability is also ensured

Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures

International audienceA small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures implemented in 32 nm CMOS technology. The DFLL control is designed so that the closed-loop system is able to cope with process variability while it rejects temperature changes and supply voltage slow variations. Therefore the DFLL is made of three main blocks, namely a Digitally Controlled Oscillator (DCO), a "sensor" that measures the frequency of the signal at the output of the DCO and a controller. A strong emphasis is set on the loop filter architecture choice and the tuning of its parameters. An analytical model of the DCO is deduced from accurate Spice simulations. The delay introduced by the sensor is also taken into account to design. From these models, an optimal and robust controller with a minimum implementation area is developed. Here, "optimal" means that the controller is computed via the minimization of a given criterion while the "robustness" capability ensures that the closed-loop system is tolerant to process and temperature variations in a given range. Therefore, performances of the closed-loop system are ensured whatever the system characteristics are in a given range

Ultra-Low-Power Wake-up Clock Design for SoC Applications

This thesis studies how to design an ultra-low-power wake-up clock circuit for SoCapplications that essentially consists of a resistor based reference circuit, switched-capacitor branch, an ultra-low-power amplifier, a VCO and a non-overlapping clockphase generator circuit. The circuit is designed in 180-nm CMOS technology usingCAD software for circuit design, layout design, pre and post-layout simulations.At first, a brief study of different clock-generation circuit architectures is made,wherein their merits and de-merits are discussed. This is followed by a study ofan ultra-low-power amplifier, ring-oscillator-based VCO, non-overlapping clockcircuits, the bias generation circuit and the current reference circuit. Additionally,a reference current chopping technique that further improves temperature stabilityis also described. Later, the report discusses the design and simulations of theactual implementation. Analysis of the design with regards to power consumption,temperature stability and layout area are carried out. The circuit operates at8.254kHz consuming 70.4nW with a temperature stability of 7.35ppm/◦C in thetemperature range of -40◦C to 75◦C. The final layout takes an area of 0.153mm2.The final design is analysed for its functionality at various process, voltage andtemperature corners. Future improvements in the current design are also discussedat the end of this report

Demodulator techniques in satellite communication systems for direct broadcast systems

This thesis is concerned with the FM demodulator techniques used in terrestrial TV receiver designs for Direct Broadcast Systems (DBS) from satellites. The various MAC/Packet schemes intended for DBS applications are described and the international standards that apply to them considered, with particular emphasis on the D2-MAC system. Noise in FM systems is discussed and a suitable threshold noise model is chosen for use in DBS TV demodulator systems. The characteristics of the various types of noise effects are considered in terms of their effect upon the TV picture. The threshold performance of a conventional FM demodulator for differing types of modulation is reviewed and it is shown how the threshold characteristic depends upon the nature of the modulation. The literature review carried out represents a significant component of the thesis and combines material from patent literature with more conventional source materials from professional journals, conferences, textbooks, etc. Some ten existing demodulator concepts that exhibit threshold extension characteristics are examined, and where relevant their potential performance in D2-MAC format systems is assessed. The demodulator characteristics that limit their performance in TV systems are identified. It is concluded that designing a threshold extension demodulator, with reliable operation, for all picture contents and for a wide range of input carrier-to-noise ratios, is a formidable task using existing design techniques. On the basis of this examination an adaptive threshold extension demodulator concept is proposed, that utilises information contained within the signal structure to achieve an improved performance over a wide range of input carrier-to-noise ratios and picture content. It is shown how the relevant signal structures may be derived from conventional (PAL, SECAM and NTSC), MAC format and all-digital television systems. Illustrations are given that show how the adaptive demodulator concept can be applied to certain existing threshold extension demodulators, enhancing their performance for television picture reception. Future trends in all-digital DBS TV systems intended ultimately for DBS applications are briefly discussed together with their demodlilation requirements

Flow detectors having mechanical oscillators, and use thereof in flow characterization systems

An improved system (100), resonator flow detector (102) and method for characterizing a fluid sample that includes o injecting a fluid sample into a mobile phase of a flow characterization system (106), and detecting a property of the fluid sample > or of a component thereof with a flow detector (102) comprising a mechanical resonator (120), preferably one that is operated at a frequency less than about 1 MHz, such as tuning fork resonator

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Development of an ultra-low field magnetic resonance imaging scanner and DC SQUID based current sensors for the investigation of hyperpolarization techniques

Kernspinresonanzspektroskopie und Kernspinresonanztomographie sind etablierte Verfahren in der Strukturanalyse und der medizinischen Bildgebung. Aufgrund der hohen Kosten bei der Anschaffung und dem Betrieb der Spektrometer und Tomographen, welche haupts{\"a}chlich aus den ben{\"o}tigten supraleitenden Elektromagneten resultieren, gibt es ein wachsendes Interesse an kosteng{\"u}nstigen Ger{\"a}ten. Spektrometer und Tomographen auf Basis von normalleitenden Elektromagneten erlauben kosteng{\"u}nstige Systeme, was jedoch aufgrund der niedrigeren Magnetfeldst{\"a}rke und einer damit einhergehenden niedrigeren Probenpolarisierung zu Lasten des Messsignals geht. Um Signalverlust teilweise zu kompensieren werden in Niederfeldsystemen Detektoren auf Basis von gleichstrombetriebenen (DC) supraleitenden Quanteninterferometern (SQUIDs) verwendet, welche eine deutlich h{\"o}here Empfindlichkeit als konventionelle Detektionsspulen aus Kupfer besitzen. Zus{\"a}tzlich bieten neuartige Hyperpolarisierungsmethoden auf Basis von Parawasserstoff, welche bei niedrigen Magnetfeldst{\"a}rken im Bereich weniger mT anwendbar sind, die M{\"o}glichkeit, die Probenpolarisierung durch die {\"U}bertragung der Spinordnung von Parawasserstoff-Kernen auf Wasserstoff-Kerne der Probe um mehrere Gr{\"o}ssenordnungen zu erh{\"o}hen. Zur erfolgreichen Hyperpolarisierung der zu untersuchenden Proben werden Polarisierungstransfer-Katalysatoren ben{\"o}tigt. In dieser Arbeit wird zum Einen die Konzeption und der Aufbau eines Ultra-Niederfeld Kernspinresonanzspektrometers/-tomographen mit einem DC SQUID basierten Magnetfeldsensor zur kontrollierten Charakterisierung von neu entwickelten Polarisierungstransfer-Katalysatoren f{\"u}r Hyperpolarisierungsanwendungen vorgestellt. Der gesamte Aufbau wurde durch weitestgehende Vermeidung von metallischen Komponenten auf m{\"o}glichst niedrige Magnetfeldrauschwerte $S_B^{1/2}$ und homogene Magnetfelder hin optimiert, was sich in einem Magnetfeldrauschen $S_B^{1/2}=1.15\,\textrm{fT/Hz}^{1/2}$ im Bereich wei{\ss}en Rauschens und Linienbreiten der Kernspinresonanz $<1\,$Hz zeigt. Zum Anderen wurden im Rahmen der Arbeit DC SQUID basierte Stromsensoren zur Erfassung der Kernspinresonanz-Signale entworfen, welche auf dem Niedertemperatur-Supraleiter Niob basieren. Dabei konnte sowohl ein Supraleiter/Normalleiter/Supraleiter (SNS) als auch auf einen Supraleiter/Isolator/Supraleiter (SIS) Herstellungsprozess zur{\"u}ckgegriffen werden. Der Stromsensorentwurf wurde an die kritische Stromdichte $j_c$ des jeweiligen Herstellungsprozesses angepasst, was in unterschiedlichen SQUID-Induktivit{\"a}ten und dadurch in verschiedenen Ankoppelschemata der Signalaufnehmer-Spulen an das SQUID resultiert. Transport- und Rauscheigenschaften wurden bei einer Temperatur von $T = 4.2\,$K bestimmt. F{\"u}r die SNS basierten Stromsensoren konnte eine Eingansempfindlichkeit $1/M_{in}=37.8\,\mu$A gefunden werden, was in Kombination mit einem Flussrauschen $S_{\Phi}^{1/2} = 590\,\textrm{n}\Phi_0\textrm{/Hz}^{1/2}$ im Bereich wei{\ss}en Rauschens zu einer Stromempfindlichkeit $S_{i}^{1/2} = 21.9\,\textrm{pA/Hz}^{1/2}$ f{\"u}hrt. Mit SIS basierten Stromsensoren konnte eine Eingansempfindlichkeit $1/M_{in}<1\,\mu$A erreicht werden. Die tats{\"a}chliche Stromempfindlichkeit konnte jedoch nicht bestimmt werden, da aufgrund von herstellungsbedingten Schichtisolationsproblemen sehr hohe Flussrauschwerte resultierten. Anhand von hyperpolarisiertem Pyridin konnte ein Signalverstärkungsfaktor von $\leq200$ gemessen werden. Daran anschlie{\ss}end wurden drei weitere Probensubstanzen untersucht, welche sowohl $^1$H- $^{19}$F-Kerne enthalten und in Hochfeldmessungen vielversprechende Resultate zeigten. Dabei zeigten zwei Probensubstanzen ein Verhalten des Polarisationstransfers, wie er gem{\"a}{\ss} der etablierten Theorie auf Basis von J-Kopplung. Die dritte Probe hingegen zeigt ein Verhalten, was nicht mit J-Kopplung der Kerne erkl{\"a}rt werden kann und auf alternative Hyperpolarisierungsmechanismen schlie{\ss}en l{\"a}sst

A space communications study Final report, 15 Sep. 1966 - 15 Sep. 1967

Investigation of signal to noise ratios and signal transmission efficiency for space communication system

Five-Level Flying Capacitor Converter used as a Static Compensator for Current Unbalances in Three-Phase Distribution Systems

This thesis presents and evaluates a solution for unbalanced current loading in three-phase distribution systems. The proposed solution uses the flying capacitor multilevel converter as its main topology for an application known as Unbalanced Current Static Compensator. The fundamental theory, controller design and prototype construction will be presented along with the experimental results. The Unbalanced Current Static Compensator main objective is the balancing of the up-stream currents from the installation point to eliminate the negative- and zero-sequence currents originated by unbalanced single-phase loads. Three separate single-phase flying capacitor converters are controlled independently using a d-q rotating reference frame algorithm to allow easier compensation of reactive power. Simulations of the system were developed in MATLAB/SIMULINK™ in order to validate the design parameters; then, testing of the UCSC prototype was performed to confirm the control algorithm functionality. Finally, experimental result are presented and analyzed