Constructivist Multi-Access Lab Approach in Teaching FPGA Systems Design with LabVIEW

Embedded systems play vital role in modern applications [1]. They can be found in autos, washing machines, electrical appliances and even in toys. FPGAs are the most recent computing technology that is used in embedded systems. There is an increasing demand on FPGA based embedded systems, in particular, for applications that require rapid time responses. Engineering education curricula needs to respond to the increasing industrial demand of using FPGAs by introducing new syllabus for teaching and learning this subject. This paper describes the development of new course material for teaching FPGA-based embedded systems design by using ‘G’ Programming Language of LabVIEW. A general overview of FPGA role in engineering education is provided. A survey of available Hardware Programming Languages for FPGAs is presented. A survey about LabVIEW utilization in engineering education is investigated; this is followed by a motivation section of why to use LabVIEW graphical programming in teaching and its capabilities. Then, a section of choosing a suitable kit for the course is laid down. Later, constructivist closed-loop model the FPGA course has been proposed in accordance with [2- 4; 80,86,89,92]. The paper is proposing a pedagogical framework for FPGA teaching; pedagogical evaluation will be conducted in future studies. The complete study has been done at the Faculty of Electrical and Electronic Engineering, Aleppo University

Design and application of reconfigurable circuits and systems

Open Acces

Teaching electronics-ICT : from focus and structure to practical realizations

We present a four-year electronics-ICT educational master program at Ghent University in Belgium. The students develop knowledge and skills from novice to experienced electronic circuit designers. In the corresponding topics, the immersion into engineering problems is deepened. The horizontal and vertical alignment of courses in the four-year master program at our university is discussed. The curriculum of the four-year master program is highly projectoriented and all topics are clustered around a well-considered set of standards. This clustering supports the logical structure of the program, with students gradually acquiring the necessary competences. All standards and their mutual interaction are extensively discussed in the paper. We also focus on four design-implement projects included in the electronics-ICT program, explicitly following CDIO-guidelines. Whereas the first-year project has a limited level of difficulty, the challenges increase significantly in the course of the next years. Students learn that product design is an iterative process on different levels, where the design strategy can be changed continuously based on important and crucial feedback. Different evaluations have demonstrated that our students are not only aware of CDIO-principles, but are also convinced of the quality of the results obtained by following the standards

Educational Policies Committee Program Proposal, College of Engineering, October 26, 2006 – Master of Science in Computer Engineering

Officials at Utah State University (USU) request approval to offer the Master of Science degree in Computer Engineering, effective Spring Semester 2007

The Megaprocessor as an Educational Tool Making the Abstract Concrete

Computer architecture courses can be difficult for students to engage with and learn from. This is because, unlike most core courses for a computer science student, learning architecture is an abstract process. To address this, universities have implemented methods for teaching course material other than purely descriptive methods. This typically means using simulations to model some aspect of a CPU or FPGA (fieldprogrammable gate array) boards for hands-on experimentation in CPU design. However, there are issues with these tools. Simulations can only cover a few topics well, are prone to being abandoned, and introduce additional abstraction layers. FPGAs, while great for advanced topics and long class projects, are often best suited for senior and graduate level students. Both methods are useful, but neither offers a tangible learning experience, which is what the Megaprocessor can provide. The Megaprocessor is a room sized, general-purpose computer made from discrete components, whose architecture is comprised of primitive logic gates with LEDs on every input and output. The entire circuitry of the Megaprocessor is transparent to the users, with its entire state visible and unabstracted. Because of these properties, it is a great learning mechanism for computer architecture education. The Megaprocessor is a tool for hands on and project-based learning that can be used to span the learning gap between simulations and FPGAs

From specialized to core course in Telecommunications degree: Experiences from digital electronic design and verification

[EN] The European Higher Education Area (EHEA) defines the competences for professional practice of a Telecommunications Engineer. The School of Telecommunication Engineering of the Universitat Politècnica de València (Valencia, Spain) provides an integrated education program consisting of a Graduate (GITST) + Master (MUIT). The GITST course offers four specialization tracks: Electronics, Telematics, Communication Systems and Multimedia for the proper acquisition of knowledge and competences of the future Telecommunications Engineers. In 2018, the graduate program has implemented a structural change in the organization of subjects for reinforcing important skills, in which a course on digital electronics design and verification (Integration of Digital Systems, ISDIGI) has been transformed into a core subject of the study plan. In this paper, we describe the methodology and adaptation of ISDIGI (i.e. a project-based learning intermediate HDL course that includes design and verification abilities) to the new GITST Curriculum. In addition, this paper describes the process of moving from specialized to core subject.Martínez Millana, A.; Liberos Mascarell, A.; Monzó Ferrer, JM.; Martínez Peiró, MA.; Martínez Pérez, JD.; Gadea Gironés, R. (2020). From specialized to core course in Telecommunications degree: Experiences from digital electronic design and verification. Editorial Universitat Politècnica de València. 229-238. https://doi.org/10.4995/INN2019.2019.10133OCS22923

Intrinsically Evolvable Artificial Neural Networks

Dedicated hardware implementations of neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, most custom hardware implementations do not support intrinsic training of these networks on-chip. The training is typically done using offline software simulations and the obtained network is synthesized and targeted to the hardware offline. The FPGA design presented here facilitates on-chip intrinsic training of artificial neural networks. Block-based neural networks (BbNN), the type of artificial neural networks implemented here, are grid-based networks neuron blocks. These networks are trained using genetic algorithms to simultaneously optimize the network structure and the internal synaptic parameters. The design supports online structure and parameter updates, and is an intrinsically evolvable BbNN platform supporting functional-level hardware evolution. Functional-level evolvable hardware (EHW) uses evolutionary algorithms to evolve interconnections and internal parameters of functional modules in reconfigurable computing systems such as FPGAs. Functional modules can be any hardware modules such as multipliers, adders, and trigonometric functions. In the implementation presented, the functional module is a neuron block. The designed platform is suitable for applications in dynamic environments, and can be adapted and retrained online. The online training capability has been demonstrated using a case study. A performance characterization model for RC implementations of BbNNs has also been presented

Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation

International audienceAs SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability