Store-and-forward CDC packet transmission in digital systems

Data transmission across clock domains is a major point of interest by ASIC designers as a limited bandwidth can be responsible for a processing power bottleneck that affects the entire system. Clock domain crossing is inherently expensive in terms of area and latency as it requires overcoming issues related to the physical nature of integrated circuit latches, in particular metastability. These issues are dangerous as they do not manifest in RTL simulation. Due to this, designers often opt for generic data synchronisation solutions that are not fully suited to the nature of the data being transferred.This dissertation presents a clock domain crossing mechanism that allows two clock domains to share a common memory to transfer packet-based data. The mechanism consists in a memory controller that coordinates commands from a push (write) domain and a pop (read) domain.The main objective of the memory controller project consists in the implementation of efficient synchronisation methods in order to eliminate the need for separate synchronisation and storage memories. In essence, the controller is an extension of an asynchronous FIFO controller with added functionality, supporting multiple virtual FIFOs and variable length data packets

Synchronous Online Philosophy Courses: An Experiment in Progress

There are two main ways to teach a course online: synchronously or asynchronously. In an asynchronous course, students can log on at their convenience and do the course work. In a synchronous course, there is a requirement that all students be online at specific times, to allow for a shared course environment. In this article, the author discusses the strengths and weaknesses of synchronous online learning for the teaching of undergraduate philosophy courses. The author discusses specific strategies and technologies he uses in the teaching of online philosophy courses. In particular, the author discusses how he uses videoconferencing to create a classroom-like environment in an online class

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness

Concurrent cell rate simulation of ATM telecommunications network.

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Working with cryptographic key information

It is important to create a cryptographic system such that the encryption system does not depend on the secret storage of the algorithm that is part of it, but only on the private key that is kept secret. In practice, key management is a separate area of cryptography, which is considered a problematic area. This paper describes the main characteristics of working with cryptographic key information. In that, the formation of keys and working with cryptographic key information are stored on external media. The random-number generator for generating random numbers used for cryptographic key generation is elucidated. To initialize the sensor, a source of external entropy, mechanism “Electronic Roulette” (biological random number), is used. The generated random bits were checked on the basis of National Institute of Standards and Technology (NIST) statistical tests. As a result of the survey, the sequence of random bits was obtained from the tests at a value of P≥0.01. The value of P is between 0 and 1, and the closer the value of P is to 1, the more random the sequence of bits is generated. This means that random bits that are generated based on the proposed algorithm can be used in cryptography to generate crypto-resistant keys

Algorithms and architectures for the multirate additive synthesis of musical tones

In classical Additive Synthesis (AS), the output signal is the sum of a large number of independently controllable sinusoidal partials. The advantages of AS for music synthesis are well known as is the high computational cost. This thesis is concerned with the computational optimisation of AS by multirate DSP techniques. In note-based music synthesis, the expected bounds of the frequency trajectory of each partial in a finite lifecycle tone determine critical time-invariant partial-specific sample rates which are lower than the conventional rate (in excess of 40kHz) resulting in computational savings. Scheduling and interpolation (to suppress quantisation noise) for many sample rates is required, leading to the concept of Multirate Additive Synthesis (MAS) where these overheads are minimised by synthesis filterbanks which quantise the set of available sample rates. Alternative AS optimisations are also appraised. It is shown that a hierarchical interpretation of the QMF filterbank preserves AS generality and permits efficient context-specific adaptation of computation to required note dynamics. Practical QMF implementation and the modifications necessary for MAS are discussed. QMF transition widths can be logically excluded from the MAS paradigm, at a cost. Therefore a novel filterbank is evaluated where transition widths are physically excluded. Benchmarking of a hypothetical orchestral synthesis application provides a tentative quantitative analysis of the performance improvement of MAS over AS. The mapping of MAS into VLSI is opened by a review of sine computation techniques. Then the functional specification and high-level design of a conceptual MAS Coprocessor (MASC) is developed which functions with high autonomy in a loosely-coupled master- slave configuration with a Host CPU which executes filterbanks in software. Standard hardware optimisation techniques are used, such as pipelining, based upon the principle of an application-specific memory hierarchy which maximises MASC throughput