78 research outputs found
Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators
In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators.
A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer
coefficients but also exhibited greater robustness to non-idealties.
Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work.
In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator.
This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio
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Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams
This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution
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A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts.
In this thesis, a wideband low-power CT ΔΣ modulator for next generation wireless applications is proposed to achieve 10-bit dynamic range within a 25 MHz signal bandwidth. On the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. On the circuit level, two-stage operational amplifiers with class-AB output stages are used to implement low-power active RC integrators. Capacitor tuning is used to compensate the variation of RC time constants. In addition, a fast current adder, an 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which was manufactured in TSMC 0.18 μm CMOS technology. The test results show that the modulator draws less than 10 mA from the 1.8 V supply voltage
Engineering Education and Research Using MATLAB
MATLAB is a software package used primarily in the field of engineering for signal processing, numerical data analysis, modeling, programming, simulation, and computer graphic visualization. In the last few years, it has become widely accepted as an efficient tool, and, therefore, its use has significantly increased in scientific communities and academic institutions. This book consists of 20 chapters presenting research works using MATLAB tools. Chapters include techniques for programming and developing Graphical User Interfaces (GUIs), dynamic systems, electric machines, signal and image processing, power electronics, mixed signal circuits, genetic programming, digital watermarking, control systems, time-series regression modeling, and artificial neural networks
PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND
The primary objective of this research work is the development of a low power single-lead ECG
analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient
gain and frequency control mechanism and a low complexity classifier for the detecting asystole,
extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the
design of a compact single-lead wearable/portable devices with ultra-low-power consumption and
in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from
hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use
an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input
ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low
power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable
amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the
contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by
external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an
efficient automatic gain control mechanism with minimal area overhead and consuming power in the
order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or
input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR),
hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter
design, the low pass cut-off frequency is prone to deviate from its nominal value across process
and temperature variations. Therefore, post-fabrication calibration is essential, before the signal
is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher
frequencies into the bandwidth
for classification of ECG signals, to switch to low resolution processing, hence saving power and
enhances battery lifetime. Another short-coming noticed in the literature published so far is that
the classification algorithm is implemented in digital domain, which turns out to be a power hungry
approach. Moreover, Although analog domain implementations of QRS complexes detection schemes
have been reported, they employ an external micro-controller to determine the threshold voltage. In
this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a
heart rate estimator is added to the above scheme. It reduces the overall system power consumption
by reducing the computational burden on the DSP. The complete proposed scheme consists of (i)
an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage,
hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient
analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia
and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes
within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis.
The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V
supply. The functionality of each of the individual blocks are successfully validated using postextraction
process corner simulations and through real ECG test signals taken from the PhysioNet
database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the
measurement results are discussed here. The analog classification scheme is successfully validated
using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac
Study of efficient transmission and reception of image-type data using millimeter waves
Evaluation of signal processing and modulation techniques for transmission and reception of image type data via millimeter wave relay satellite
Differential encoding techniques applied to speech signals
The increasing use of digital communication systems has
produced a continuous search for efficient methods of speech
encoding.
This thesis describes investigations of novel differential
encoding systems. Initially Linear First Order DPCM systems
employing a simple delayed encoding algorithm are examined.
The systems detect an overload condition in the encoder, and
through a simple algorithm reduce the overload noise at the
expense of some increase in the quantization (granular) noise.
The signal-to-noise ratio (snr) performance of such d codec has
1 to 2 dB's advantage compared to the First Order Linear DPCM
system.
In order to obtain a large improvement in snr the high
correlation between successive pitch periods as well as the
correlation between successive samples in the voiced speech
waveform is exploited. A system called "Pitch Synchronous
First Order DPCM" (PSFOD) has been developed. Here the difference
Sequence formed between the samples of the input sequence in the
current pitch period and the samples of the stored decoded
sequence from the previous pitch period are encoded. This
difference sequence has a smaller dynamic range than the original
input speech sequence enabling a quantizer with better resolution
to be used for the same transmission bit rate. The snr is increased
by 6 dB compared with the peak snr of a First Order DPCM codea.
A development of the PSFOD system called a Pitch Synchronous
Differential Predictive Encoding system (PSDPE) is next investigated.
The principle of its operation is to predict the next sample in
the voiced-speech waveform, and form the prediction error which
is then subtracted from the corresponding decoded prediction
error in the previous pitch period. The difference is then
encoded and transmitted. The improvement in snr is approximately
8 dB compared to an ADPCM codea, when the PSDPE system uses an
adaptive PCM encoder. The snr of the system increases further
when the efficiency of the predictors used improve. However,
the performance of a predictor in any differential system is
closely related to the quantizer used. The better the quantization
the more information is available to the predictor and the better
the prediction of the incoming speech samples. This leads
automatically to the investigation in techniques of efficient
quantization. A novel adaptive quantization technique called
Dynamic Ratio quantizer (DRQ) is then considered and its theory
presented. The quantizer uses an adaptive non-linear element
which transforms the input samples of any amplitude to samples
within a defined amplitude range. A fixed uniform quantizer
quantizes the transformed signal. The snr for this quantizer
is almost constant over a range of input power limited in practice
by the dynamia range of the adaptive non-linear element, and it
is 2 to 3 dB's better than the snr of a One Word Memory adaptive
quantizer.
Digital computer simulation techniques have been used widely
in the above investigations and provide the necessary experimental
flexibility. Their use is described in the text
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