7 research outputs found
An Implantable Phase Locked Loop MEMS Based Readout System for Heart Transplantation
An implantable readout circuit using a MEMS pressure sensor has been designed and implemented to monitor the heart activity after heart transplant surgery. It features a time domain architecture using two identical voltage-controlled oscillators and phase locked loop circuits. The circuit was implemented in a 65 nm CMOS technology with 1 V power supply. It consumes 100 lW power and provides a digital output that is proportional to the analog sensor input with a bandwidth of up to 4 kHz. The SNR of the system is 53 dB. Measurements show the operation of the readout chip with the MEMS sensor
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS : part 1: basic principles
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs. The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling. Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues. Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance. This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date
Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays
Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging
and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through
the skull has prevented ultrasound imaging of the brain. This research is a prime
step toward implantable wireless microsystems that use ultrasound to image the
brain by bypassing the skull. These microsystems offer autonomous scanning
(beam steering and focusing) of the brain and transferring data out of the brain for
further processing and image reconstruction.
The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their
associated integrated electronics in terms of electrical power transfer and acoustic
reflection which would potentially lead to more efficient and high-performance
systems.
A fully wireless architecture for ultrasound imaging is demonstrated for the
first time. An on-chip programmable transmit (TX) beamformer enables phased
array focusing and steering of ultrasound waves in the transmit mode while its
on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB)
uplink transmitter minimizes the effect of path loss on the transmitted image data
out of the brain. A single-chip application-specific integrated circuit (ASIC) is de-
signed to realize the wireless architecture and interface with array elements, each
of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser,
a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building
blocks.
Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a
power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo
differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems.
In addition, the effect of matching and electrical termination on CMUT array
elements is explored leading to new interface structures to improve bandwidth
and sensitivity of CMUT arrays in different operation regions. Comprehensive
analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones
Mención Internacional en el tÃtulo de doctorThis thesis focuses on the development of capacitive sensor readout circuits
and data converters based on frequency-encoding. This research
has been motivated by the needs of consumer electronics industry, which
constantly demands more compact readout circuit for MEMS microphones
and other sensors. Nowadays, data acquisition is mainly based
on encoding signals in voltage or current domains, which is becoming
more challenging in modern deep submicron CMOS technologies.
Frequency-encoding is an emerging signal processing technique based
on encoding signals in the frequency domain. The key advantage of
this approach is that systems can be implemented using mostly-digital
circuitry, which benefits from CMOS technology scaling. Frequencyencoding
can be used to build phase referenced integrators, which can
replace classical integrators (such as switched-capacitor based integrators)
in the implementation of efficient analog-to-digital converters and
sensor interfaces. The core of the phase referenced integrators studied in
this thesis consists of the combination of different oscillator topologies
with counters and highly-digital circuitry.
This work addresses two related problems: the development of capacitive
MEMS sensor readout circuits based on frequency-encoding, and the
design and implementation of compact oscillator-based data converters
for audio applications.
In the first problem, the target is the integration of the MEMS sensor
into an oscillator circuit, making the oscillation frequency dependent on
the sensor capacitance. This way, the sound can be digitized by measuring
the oscillation frequency, using digital circuitry. However, a MEMS
microphone is a complex structure on which several parasitic effects can
influence the operation of the oscillator. This work presents a feasibility
analysis of the integration of a MEMS microphone into different oscillator
topologies. The conclusion of this study is that the parasitics of the
MEMS limit the performance of the microphone, making it inefficient.
In contrast, replacing conventional ADCs with frequency-encoding based
ADCs has proven a very efficient solution, which motivates the next
problem.
In the second problem, the focus is on the development of high-order
oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical
integrators and phase referenced integrators has been studied, followed
by an overview of state-of-art oscillator-based converters. Then,
a procedure to replace classical integrators by phase referenced integrators
is presented, including a design example of a second-order oscillator based
Sigma-Delta modulator. Subsequently, the main circuit impairments that
limit the performance of this kind of implementations, such as phase
noise, jitter or metastability, are described.
This thesis also presents a methodology to evaluate the impact of
phase noise and distortion in oscillator-based systems. The proposed
method is based on periodic steady-state analysis, which allows the rapid
estimation of the system dynamic range without resorting to transient
simulations. In addition, a novel technique to analyze the impact of
clock jitter in Sigma-Delta modulators is described.
Two integrated circuits have been implemented in 0.13 μm CMOS
technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder
noise shaping using only oscillators and digital circuitry. The first
testchip shows a malfunction in the digital circuitry due to the complexity
of the multi-bit counters. The second chip, implemented using
single-bit counters for simplicity, shows second-order noise shaping and
reaches 103 dB-A of dynamic range in the audio bandwidth, occupying
only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces
para sensores capacitivos basados en codificación en frecuencia. Esta
investigación está motivada por las necesidades de la industria, que constantemente
demanda reducir el tamaño de este tipo de circuitos. Hoy en
dÃa, la adquisición de datos está basada principalmente en la codificación
de señales en tensión o en corriente. Sin embargo, la implementación
de este tipo de soluciones en tecnologÃas CMOS nanométricas presenta
varias dificultades.
La codificación de frecuencia es una técnica emergente en el procesado
de señales basada en codificar señales en el dominio de la frecuencia.
La principal ventaja de esta alternativa es que los sistemas pueden implementarse
usando circuitos mayoritariamente digitales, los cuales se
benefician de los avances de la tecnologÃa CMOS. La codificación en
frecuencia puede emplearse para construir integradores referidos a la
fase, que pueden reemplazar a los integradores clásicos (como los basados
en capacidades conmutadas) en la implementación de conversores
analógico-digital e interfaces de sensores. Los integradores referidos a la
fase estudiados en esta tesis consisten en la combinación de diferentes
topologÃas de osciladores con contadores y circuitos principalmente digitales.
Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos
de lectura para sensores MEMS capacitivos basados en codificación
temporal, y el diseño e implementación de conversores de datos
compactos para aplicaciones de audio basados en osciladores.
En el primer caso, el objetivo es la integración de un sensor MEMS
en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado
midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos
en su mayor parte digitales. Sin embargo, un micrófono MEMS es
una estructura compleja en la que múltiples efectos parasÃticos pueden
alterar el correcto funcionamiento del oscilador. Este trabajo presenta
un análisis de la viabilidad de integrar un micrófono MEMS en diferentes
topologÃas de oscilador. La conclusión de este estudio es que los parasÃticos
del MEMS limitan el rendimiento del micrófono, causando que esta
solución no sea eficiente. En cambio, la implementación de conversores
analógico-digitales basados en codificación en frecuencia ha demostrado
ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente
problema.
La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado
la equivalencia entre los integradores clásicos y los integradores
referidos a la fase, seguido de una descripción de los conversores basados
en osciladores publicados en los últimos años. A continuación se
presenta un procedimiento para reemplazar integradores clásicos por integradores
referidos a la fase, incluyendo un ejemplo de diseño de un
modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente
se describen los principales problemas que limitan el rendimiento de este
tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad.
Esta tesis también presenta un nuevo método para evaluar el impacto
del ruido de fase y de la distorsión en sistemas basados en osciladores. El
método propuesto está basado en simulaciones PSS, las cuales permiten
la rápida estimación del rango dinámico del sistema sin necesidad de
recurrir a simulaciones temporales. Además, este trabajo describe una
nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta.
En esta tesis se han implementado dos circuitos integrados en tecnologÃa
CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los
moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han
sido diseñados para producir conformación espectral de ruido de segundo
orden, usando únicamente osciladores y circuitos mayoritariamente digitales.
El primer chip ha mostrado un error en el funcionamiento de los
circuitos digitales debido a la complejidad de las estructuras multi-bit
utilizadas. El segundo chip, implementado usando contadores de un solo
bit con el fin de simplificar el sistema, consigue conformación espectral
de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el
ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en IngenierÃa Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus
Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS
An energy-efficient and supply-and temperature-resilient resistive sensor interface in 130-nm CMOS technology is presented. Traditionally resistive sensors are interfaced with a Wheatstone bridge and an amplitude-based analog-to-digital converter (ADC). However, both the unbalanced Wheatstone bridge and the ADC are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture that combines the advantage of energy-efficient sensing with highly improved overall PSRR and temperature resilience in one circuit. The prototyped circuit has a noise-frequency- independent PSRR of 52 dB, even for supply-noise amplitudes up to +10 dB FS. The maximum absolute output error in a supply voltage range of 0.85-1.15 V is only 0.7%, while the maximum absolute output error in a temperature range of 100 °C is only 0.56% or 56 ppm/°C. The complete interface is prototyped in 130-nm CMOS and consumes 124.5 μW from a 1-V supply with a 10-kHz input bandwidth and 10.4-b resolution and 8.9-b linearity, resulting in a state-of-the-art sensor figure of merit of 13.03 pJ/bit-conversion. © 2013 IEEE.status: publishe