Functional Description and Control Design of Modular Multilevel Converters:Towards Energy Storage Applications for Traction Networks

The security of supply is becoming an important concern in the energy supply of the railway networks operated at 16.7âHz. This situation calls for the improvement of the interconnection with the 50âHz grid and creates a need for ancillary services, especially in relation to power quality. To these ends, Modular Multilevel Converters (MMC) are highly attractive as they are ideally suited for the corresponding voltage and power levels and are sufficiently versatile to adapt easily to the numerous applications affected by these needs. Besides, there attractiveness can be further increased if energy storage is embedded inside the converters, which are then able to provide a broad range of ancillary services. Practically, such a perspective is enabled by the fact that the submodules can directly integrate storage in a distributed manner, essentially limiting design concerns to control issues. By 2014, MMCs have been adopted by most major power electronics manufacturers (ABB, Siemens, Alstom, etc.) and constitute a rapidly expanding topic, drawing the attention of numerous academic research groups worldwide. This illustrates the breakthrough represented by this technology, which is notably due to the fact that their modular nature imposes operating principles that are fundamentally different from those of conventional structures, but what also allows unprecedented flexibility and scalability. Being given the numerous ongoing industrial projects in relation to railways, the relevance of MMCs in these applications is already largely proven. However, the integration of split storage in MMCs has still received only little attention. This thesis will even propose the use of hybrid split storage, which has apparently not been studied at all. In both cases, the development of energy management mechanisms has apparently not been addressed yet and the control design as a whole is also limited to few developments only. On the other hand, there are already numerous control solutions for the cases without storage, among which it is sometimes difficult to make wise choices. In this context, before adding energy storage (and its associated management mechanisms) to already complex control problems, it is important to rely on a sound basis, what is the main motivation for this thesis to develop a set of tools that can allow to take a step back on the control design in general. Firstly, this thesis proposes different representations of MMCs, providing a macroscopic view of their behavior and allowing a new interpretation of their principles of operation. As it will be seen, these results are useful to both control design and system engineering purposes. Secondly, using the principles of the Energetic Macroscopic Representation (EMR), this work presents a methodology for the systematic control design of MMCs, based on the functional inversion of a system model. Finally, the obtained results are validated on known structures before being extended to other converter systems including energy storage. In parallel to these developments, several digressions are also made to comment on the issues related to the control hardware and on the possible applications of energy storage in railways. In the end, these developments are expected to contribute to improve the modularization of the control in general, which is one of the possible ways to provide maximum flexibility, speed and effectiveness in the overall design of MMC systems for all types of applications

The STiC ASIC High Precision Timing with Silicon Photomultipliers

In recent years, Silicon Photomultipliers are being increasingly used for Time of Flight measurements in particle detectors. To utilize the high intrinsic time resolution of these sensors in detector systems, the development of specialized, highly integrated readout electronics is required. In this thesis, a mixed-signal application specific integrated circuit, named STiC, has been developed, characterized and integrated in a detector system. STiC has been specifically designed for high precision timing measurements with SiPMs, and is in particular dedicated to the EndoTOFPET-US project, which aims to achieve a coincidence time resolution of 200 ps FWHM and an energy resolution of less than 20% in an endoscopic positron emission tomography system. The chip integrates 64 high precision readout channels for SiPMs together with a digital core logic to process, store and transfer the recorded events to a data acquisition system. The performance of the chip has been validated in coincidence measurements using detector modules consisting of 3.1×3.1×15 mm³ LYSO crystals coupled to Silicon Photomultipliers from Hamamatsu. The measurements show an energy resolution of 15% FWHM for the detection of 511keV photons. A coincidence time resolution of 213ps FWHM has been measured, which is among the best resolution values achieved to date with this detector topology. STiC has been integrated in the EndoTOFPET-US detector system and has been chosen as the baseline design for the readout of SiPM sensors in the Mu3e experiment

The CMS experiment at the CERN LHC

The Compact Muon Solenoid (CMS) detector is described. The detector operates at the Large Hadron Collider (LHC) at CERN. It was conceived to study proton-proton (and leadlead) collisions at a centre-of-mass energy of 14 TeV (5.5 TeV nucleon-nucleon) and at luminosities up to 1034 cm-2s-1 (1027 cm-2s-1). At the core of the CMS detector sits a high-magnetic field and large-bore superconducting solenoid surrounding an all-silicon pixel and strip tracker, a lead-tungstate scintillating-crystals electromagnetic calorimeter, and a brass-scintillator sampling hadron calorimeter. The iron yoke of the flux-return is instrumented with four stations of muon detectors covering most of the 4π solid angle. Forward sampling calorimeters extend the pseudorapidity coverage to high values (|η| ≤ 5) assuring very good hermeticity. The overall dimensions of the CMS detector are a length of 21.6 m, a diameter of 14.6 m and a total weight of 12500 t

The Miniaturization of the AFIT Random Noise Radar

Advances in technology and signal processing techniques have opened the door to using an UWB random noise waveform for radar imaging. This unique, low probability of intercept waveform has piqued the interest of the U.S. DoD as well as law enforcement and intelligence agencies alike. While AFIT\u27s noise radar has made significant progress, the current architecture needs to be redesigned to meet the space constraints and power limitations of an aerial platform. This research effort is AFIT\u27s first attempt at RNR miniaturization and centers on two primary objectives: 1) identifying a signal processor that is compact, energy efficient, and capable of performing the demanding signal processing routines and 2) developing a high-speed correlation algorithm that is suited for the target hardware. A correlation routine was chosen as the design goal because of its importance to the noise radar\u27s ability to estimate the presence of a return signal. Furthermore, it is a computationally intensive process that was used to determine the feasibility of the processing component. To determine the performance of the proposed algorithm, results from simulation and experiments involving representative hardware were compared to the current system. Post-implementation reports of the FPGA-based correlator indicated zero timing failures, less than a Watt of power consumption, and a 44% utilization of the Virtex-5\u27s logic resources

Management and Protection of High-Voltage Direct Current Systems Based on Modular Multilevel Converters

The electrical grid is undergoing large changes due to the massive integration of renewable energy systems and the electrification of transport and heating sectors. These new resources are typically non-dispatchable and dependent on external factors (e.g., weather, user patterns). These two aspects make the generation and demand less predictable, facilitating a larger power variability. As a consequence, rejecting disturbances and respecting power quality constraints gets more challenging, as small power imbalances can create large frequency deviations with faster transients. In order to deal with these challenges, the energy system needs an upgraded infrastructure and improved control system. In this regard, high-voltage direct current (HVdc) systems can increase the controllability of the power system, facilitating the integration of large renewable energy systems. This thesis contributes to the advancement of the state of the art in HVdc systems, addressing the modeling, control and protection of HVdc systems, adopting modular multilevel converter (MMC) technology, with focus in providing services to ac systems. HVdc system control and protection studies need for an accurate HVdc terminal modeling in largely different time frames. Thus, as a first step, this thesis presents a guideline for the necessary level of deepness of the power electronics modeling with respect to the power system problem under study. Starting from a proper modeling for power system studies, this thesis proposes an HVdc frequency regulation approach, which adapts the power consumption of voltage-dependent loads by means of controlled reactive power injections, that control the voltage in the grid. This solution enables a fast and accurate load power control, able to minimize the frequency swing in asynchronous or embedded HVdc applications. One key challenge of HVdc systems is a proper protection system and particularly dc circuit breaker (CB) design, which necessitates fault current analysis for a large number of grid scenarios and parameters. This thesis applies the knowledge developed in the modeling and control of HVdc systems, to develop a fast and accurate fault current estimation method for MMC-based HVdc system. This method, including the HVdc control, achieved to accurately estimate the fault current peak value and slope with very small computational effort compared to the conventional approach using EMT-simulations. This work is concluded introducing a new protection methodology, that involves the fault blocking capability of MMCs with mixed submodule (SM) structure, without the need for an additional CB. The main focus is the adaption of the MMC topology with reduced number of bipolar SM to achieve similar fault clearing performance as with dc CB and tolerable SM over-voltage

Power Electronics Applications in Renewable Energy Systems

The renewable generation system is currently experiencing rapid growth in various power grids. The stability and dynamic response issues of power grids are receiving attention due to the increase in power electronics-based renewable energy. The main focus of this Special Issue is to provide solutions for power system planning and operation. Power electronics-based devices can offer new ancillary services to several industrial sectors. In order to fully include the capability of power conversion systems in the network integration of renewable generators, several studies should be carried out, including detailed studies of switching circuits, and comprehensive operating strategies for numerous devices, consisting of large-scale renewable generation clusters

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities