772 research outputs found
Optical Flow and Surface Interpolation in Resistive Networks: Algorithms and Analog VLSI Chips
To us, and to other biological organisms, vision seems effortless. We open our eyes and we "see" the world in all its color, brightness, and movement. Flies, frogs, cats, and humans can all equally well perceive a rapidly changing environment and act on it. Yet, we have great difficulties when trying to endow our machines with similar abilities. In this article, we describe
recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain "cost" functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. For instance, as
detailed in this chapter, we can compute the optical flow by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. These networks, which are implemented in subthreshold, analog, complementary metal oxide semiconductor (CMOS) very
large scale integrated (VLSI) circuits, are very attractive for their technological potential
FEEDFORWARD ARTIFICIAL NEURAL NETWORK DESIGN UTILISING SUBTHRESHOLD MODE CMOS DEVICES
This thesis reviews various previously reported techniques for simulating artificial
neural networks and investigates the design of fully-connected feedforward networks
based on MOS transistors operating in the subthreshold mode of conduction as they are
suitable for performing compact, low power, implantable pattern recognition systems.
The principal objective is to demonstrate that the transfer characteristic of the devices
can be fully exploited to design basic processing modules which overcome the linearity
range, weight resolution, processing speed, noise and mismatch of components
problems associated with weak inversion conduction, and so be used to implement
networks which can be trained to perform practical tasks.
A new four-quadrant analogue multiplier, one of the most important cells in the
design of artificial neural networks, is developed. Analytical as well as simulation
results suggest that the new scheme can efficiently be used to emulate both the synaptic
and thresholding functions. To complement this thresholding-synapse, a novel
current-to-voltage converter is also introduced. The characteristics of the well known
sample-and-hold circuit as a weight memory scheme are analytically derived and
simulation results suggest that a dummy compensated technique is required to obtain the
required minimum of 8 bits weight resolution. Performance of the combined load and
thresholding-synapse arrangement as well as an on-chip update/refresh mechanism are
analytically evaluated and simulation studies on the Exclusive OR network as a
benchmark problem are provided and indicate a useful level of functionality.
Experimental results on the Exclusive OR network and a 'QRS' complex detector
based on a 10:6:3 multilayer perceptron are also presented and demonstrate the potential
of the proposed design techniques in emulating feedforward neural networks
Proceedings of the Cold Electronics Workshop
The benefits and problems of the use of cold semiconductor electronics and the research and development effort required to bring cold electronics into more widespread use were examined
Computing motion using analog and binary resistive networks
The authors describe recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain 'cost' functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. The optical flow is computed by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. The authors believe that these networks, which they implemented in complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuits, represent plausible candidates for biological vision systems
Dynamic Power Management for Neuromorphic Many-Core Systems
This work presents a dynamic power management architecture for neuromorphic
many core systems such as SpiNNaker. A fast dynamic voltage and frequency
scaling (DVFS) technique is presented which allows the processing elements (PE)
to change their supply voltage and clock frequency individually and
autonomously within less than 100 ns. This is employed by the neuromorphic
simulation software flow, which defines the performance level (PL) of the PE
based on the actual workload within each simulation cycle. A test chip in 28 nm
SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled
from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct
PLs. By measurement of three neuromorphic benchmarks it is shown that the total
PE power consumption can be reduced by 75%, with 80% baseline power reduction
and a 50% reduction of energy per neuron and synapse computation, all while
maintaining temporary peak system performance to achieve biological real-time
operation of the system. A numerical model of this power management model is
derived which allows DVFS architecture exploration for neuromorphics. The
proposed technique is to be used for the second generation SpiNNaker
neuromorphic many core system
Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS
In questo lavoro si presenta una metodologia di
progettazione elettronica a livello di sistema,
affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su
campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di
equazioni atti a selezionare le configurazione di
interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre,
il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
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