Area Efficient Level Sensitive Flip-Flops – A Performance Comparison

Due to increased demand of portable and battery operated devices, ultra-low power and high speed devices with less area requirement are important nowadays. Latch is the basic element for all the sequential circuits. This paper presents comparison of various circuits of D latch on the basis of power consumption, area efficiency and delay. Basically in these latches transmission gates are replaced by pass transistors to reduce the transistor count. Comparison results indicate that latch design with least transistor count is the best choice for portable applications. Keywords: area efficient, latch, sub-threshold region, pass transistor, low power, level sensitive flip-flops, flip-flops

Low Power 6-Transistor Latch Design for Portable Devices

The latest advances in mobile battery-powered devices such as the Personal Digital Assistant (PDA) and mobile phones have set new goals in digital VLSI design. The portable devices require high speed and low power consumption. Even low power consumption is the dominant requirement and to do so speed can be compromised. In this paper a novel area efficient latch design is proposed. The simulation results show that the proposed design with less transistor count is better choice for low power and high speed portable applications. Keywords: Latch, Low power, Portable, 8T, 6T, Power consumption, Delay

Low voltage high bandwidth self-biased high swing cascode current mirror

A low voltage self-biased high swing cascode current mirror (SHCCM) with improved bandwidth has been proposed. The recently reported SHCCM architecture use the bulk-driven quasi-floating gate (BDQFG) MOS transistors to enhance the effective transconductance which improves the current mirror input resistance and bandwidth range over the same architecture realized using bulk-driven MOS transistors. To further improve the bandwidth the proposed BDQFG based SHCCM uses two resistances which makes the current mirror frequency response free from input capacitors and also reduces the parasitic capacitance effect which results in increased bandwidth with an advantage of having no degradation in other performance parameters of current mirror. The proposed current mirror operates well for input current range from 0 to 200 μA with good linearity and shows the bandwidth of 298 MHz (i.e., 1.6 times over prior reported BDQFG based SHCCM). The observed input and output resistance is 306 Ω and 165 kΩ, respectively. Further, the THD analysis is carried to prove the robustness of proposed current mirror. The complete analysis is performed on UMC 0.18 μm technology using HSpice

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9x Lower Energy/Access

This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9 × lower energy/access when compared with an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.Texas Instruments Incorporate

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver

This paper demonstrates a four-channel transceiver chip for medical ultrasonic imaging, interfacing to the capacitive micromachined ultrasonic transducers (CMUTs). The high-voltage transmitter (Tx) uses a three-level pulse-shaping technique with charge recycling to improve the power efficiency. The design requires minimum off-chip components and is scalable for more channels. The receiver is implemented with a transimpedance amplifier (TIA) topology and is optimized for tradeoffs between noise, bandwidth, and power dissipation. The test chip is characterized with both acoustic and electrical measurements. Comparing the three-level pulser against traditional two-level pulsers, the measured Tx efficiency shows 56%, 50%, and 43% more acoustic power delivery with the same total power dissipation at 2.5, 3.3, and 5.0 MHz, respectively. The CMUT receiver achieves the lowest noise efficiency factor compared with that of the literature (2.1 compared to a previously reported lowest of 3.6, in units of mPA ·√(mW/Hz). In addition, the transceiver chip is tested as a complete system for medical ultrasound imaging applications, in experiments including Tx beamformation, pulse-echo channel response characterization, and ultrasonic Doppler flow rate detection.Semiconductor Research Corporation. Focus Center for Circuit and System Solutions (C2S2

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than [H.264 over AVC] to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm[superscript 2] in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 [nJ over pixel] of normalized system power.Texas Instruments Incorporate