Low Power 6-Transistor Latch Design for Portable Devices

Abstract

The latest advances in mobile battery-powered devices such as the Personal Digital Assistant (PDA) and mobile phones have set new goals in digital VLSI design. The portable devices require high speed and low power consumption. Even low power consumption is the dominant requirement and to do so speed can be compromised. In this paper a novel area efficient latch design is proposed. The simulation results show that the proposed design with less transistor count is better choice for low power and high speed portable applications. Keywords: Latch, Low power, Portable, 8T, 6T, Power consumption, Delay