Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Electrochemical sensor system architecture using the CMOS-MEMS technology for cytometry applications

This thesis presents the development process of an integrated sensor-system-on-chip for recording the parameters of blood cells. The CMOS based device consists of the two flow-through sensor arrays, stacked one on top of the other. The sensors are able to detect the biological cell in terms of its physical size and the surface charge on a cell’s membrane. The development of the measurement system was divided into several stages these were to design and implement the two sensor arrays complemented with readout circuitry onto a single CMOS chip to create an on-chip membrane with embedded flow-through micro-channels by a CMOS compatible post-processing techniques to encapsulate and hermeti-cally package the device for liquid chemistry experiments, to test and characterise the two sensor arrays together with readout electronics, to develop control and data acquisition software and to detect the biological cells using the complete measurement system. Cy-tometry and haematology fields are closely related to the presented work, hence it is envis-aged that the developed technology enables further integration and miniaturisation of the biomedical instrumentation. The two vertically stacked 4 x 4 flow-through sensor arrays, embedded into an on-chip membrane, were implemented in a single silicon chip device together with a readout circuitry for each of the sensor sets. To develop a CMOS-MEMS device the design and fabrication was carried out using a commercial process design kit (0.35 µm 4-Metal, 2-Poly, CMOS) as well as the foundry service. Thereafter the device was post-processed in-house to develop the on-chip membrane and open the sensing micro-apertures. The two types of sensor were integrated on the silicon dice for multi-parametric characterisation of the analyte. To read the cell membrane charge the ion sensitive field effect transistor (ISFET) was utilised and for cell size (volume) detection an impedance sensor (Coulter counter) was used. Both sensors rely on a flow-through mode of operation, hence the constant flow of the analyte sample could be maintained. The Coulter counter metal electrode was exposed to the solution, while the ISFET floating gate electrode maintained contact with the analyte through a charge sensitive membrane constructed of a dielectric material (silicon dioxide) lining the inside of the micro-pore. The outside size of each of the electrodes was 100 µm x 100 µm and the inside varied from 20 µm x 20 µm to 58 µm x 58 µm. The sense aperture size also varied from 10 µm x 10 µm to 16 µm x 16 µm. The two stacked micro-electrode arrays were layed out on an area of 5002 µm2. The CMOS-MEMS device was fit into a custom printed circuit board (PCB) chip carrier, thereafter insulated and hermetically packaged. Microfluidic ports were attached to the packaged module so that the analyte can be introduced and drained by a flow-through mode of operation. The complete microfluidic system and packaging was assembled and thereafter evaluated for correct operation. Undisturbed flow of the analyte solution is es-sential for the sensor operation. This is related to the fact that the electrochemical response of both sensors depends on the analyte flow through the sense micro-apertures thus any aggregation of the sample within the microfluidic system would cause clogging of the mi-cro-pores. The on-chip electronic circuitry was characterised, and after comparison with the simulated results found to be within an error margin of what enables it for reliable sensor signal readout. The measurement system is automated by software control so that the bias parame-ters can be set precisely, it also helped while error debugging. Analogue signals from the two sensor arrays were acquired, later processed and stored by a data acquisition system. Both control and data capture systems are implemented in a high level programming lan-guage. Furthermore both are integrated and operated in a one window based graphical user interface (GUI). A fully functional measurement system was used as a flow-through cytometer for living cells detection. The measurements results showed that the system is capable of single cell detection and on-the-fly data display

Advanced gate stacks for nano-scale CMOS technology

Ph.DDOCTOR OF PHILOSOPH

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Lanthanoid based materials in advanced CMOS technology

Ph.DDOCTOR OF PHILOSOPH

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Three-dimensional field-effect transistors with top-down and bottom-up nanowire-array channels

This dissertation research effort explores new transistor topologies using three-dimensional nanowire (NW)-array channels formed by both bottom-up and top-down synthesis. The bottom-up NW research centers on the Au-catalyzed planar GaAs NW assembly discovered at the University of Illinois Urbana-Champaign (UIUC). The top-down NW research approach involves plasma etching of an emerging wide-bandgap material, Gallium Oxide (Ga2O3), to make arrays of NW channels (or fins) for high-power electronics. Bottom-up AlGaAs/GaAs heterostructure core-shell planar NWs are demonstrated on a wafer scale with excellent yield. Their placement is determined by lithographically patterning an array of Au seeds on semi-insulating GaAs substrate. The GaAs NWs assemble by lateral epitaxy via a vapor-liquid-solid mechanism and align in parallel arrays as a result of the (100) GaAs crystal plane orientation; then, a thin-film AlGaAs layer conforms to the GaAs NWs to form AlGaAs/GaAs NW high-electron mobility channels. Radio frequency (RF) transistors are fabricated and show excellent dc and high-frequency performance. An fmax > 75 GHz with 104 is measured which is superior compared to carbon-based nanoelectronics and “spin-on III-V NWs”. A comprehensive small-signal model is used to extract the contributing and limiting factors to the RF performance of AlGaAs/GaAs NW-array transistors and predict future performance. Finally, a process is developed to show that III-V NWs on sacrificial epitaxial templates can be transferred to arbitrary substrates. Top-down NWs were formed from Sn-doped Ga2O3 homoepitaxially grown on semi-insulating beta-phase Ga2O3 substrates by metal-organic vapor phase epitaxy. First, conventional planar transistors were fabricated from a sample set to characterize and understand the electrical performance as a function of Sn-doping and epitaxial channel thickness. Second, the high-critical field strength was evaluated to highlight the benefit of using Ga2O3 as a disruptive technology to GaN and SiC. Lastly, the planar transistor results feed into a design for a top-down NW-array transistor. The Ga2O3 NW-arrays were formed by BCl3 plasma etching. A new wrap-gate transistor demonstrates normally-off (enhancement-mode) operation with a high breakdown voltage exceeding 600 V which is superior to any transistor using a 3D channel

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid approaches where other technologies add to the CMOS performance, while maintaining a back-bone of CMOS logic. Ferro-electricity in ultra-thin films has been investigated as a credible candidate for nonvolatile memory thanks to the bistability of polarization. 1 transistor (1T) ferroelectric memory cells have been proposed and experimentally studied in order to reduce the size of 1T-1C (1Transistor-1Capacitor) design with consequent advantages in terms of size, read-out operation and costs. More recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in order to lower the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Oxide Semiconductor Field Effect Transistors, MOSFETs. The objective of this thesis is to study the ferroelectric transistor performance for both memory and switch application. For this purpose different Ferroelectric Field Effect Transistors, Fe-FETs, structures have been designed, fabricated and characterized. An organic ferroelectric polymer, vinylidene fluoride trifluorethylene, P(VDF-TrFE), of 100nm and 40nm thickness has been successfully integrated into the gate stack of bulk and SOI MOSFET and, later, on a Tunnel FET, TFET, structure. The 1T ferroelectric FET memory cells have shown a programming time in the order of ms at 9V as programming voltage. The retention of a few seconds, however, is the main limiting factor for the usage of this device for NV-memory applications. The retention failure mechanisms have been studied and investigated for future improvement. For the first time this work experimentally demonstrates that a subthreshold swing lower than 60mv/dec can be achieved in a ferroelectric transistor thanks to the voltage amplification arising from the ferroelectric material. This unique finding has been first measured in a 40nm P(VDF-TrFE)/10nm SiO2 gate stack MOSFET and then, confirmed, in a 100nm P(VDF-TrFE)/10nm SiO2 gate MOSFET with an intermediate contact between the two dielectrics. This internal node contact allows the study of the voltage amplification due to the ferroelectric material. Finally a temperature study of the performance of a ferroelectric Fully Depleted Silicon on Insulator, FD SOI, transistor has been done. A model based on Landau's theory has been carried out and it has been experimentally validated for both the subthreshold and the strong inversion regions. It has been demonstrated for the first time that, because of the divergence of the ferroelectric permittivity at the Curie temperature, Tc, a ferroelectric transistor has a maximum and a minimum, respectively of its transconductance and subthreshold swing, at Tc