Endoscopic image analysis of aberrant crypt foci

Tese de Mestrado Integrado. Bioengenharia. Faculdade de Engenharia. Universidade do Porto. 201

Compilation Techniques for High-Performance Embedded Systems with Multiple Processors

Institute for Computing Systems ArchitectureDespite the progress made in developing more advanced compilers for embedded systems, programming of embedded high-performance computing systems based on Digital Signal Processors (DSPs) is still a highly skilled manual task. This is true for single-processor systems, and even more for embedded systems based on multiple DSPs. Compilers often fail to optimise existing DSP codes written in C due to the employed programming style. Parallelisation is hampered by the complex multiple address space memory architecture, which can be found in most commercial multi-DSP configurations. This thesis develops an integrated optimisation and parallelisation strategy that can deal with low-level C codes and produces optimised parallel code for a homogeneous multi-DSP architecture with distributed physical memory and multiple logical address spaces. In a first step, low-level programming idioms are identified and recovered. This enables the application of high-level code and data transformations well-known in the field of scientific computing. Iterative feedback-driven search for “good” transformation sequences is being investigated. A novel approach to parallelisation based on a unified data and loop transformation framework is presented and evaluated. Performance optimisation is achieved through exploitation of data locality on the one hand, and utilisation of DSP-specific architectural features such as Direct Memory Access (DMA) transfers on the other hand. The proposed methodology is evaluated against two benchmark suites (DSPstone & UTDSP) and four different high-performance DSPs, one of which is part of a commercial four processor multi-DSP board also used for evaluation. Experiments confirm the effectiveness of the program recovery techniques as enablers of high-level transformations and automatic parallelisation. Source-to-source transformations of DSP codes yield an average speedup of 2.21 across four different DSP architectures. The parallelisation scheme is – in conjunction with a set of locality optimisations – able to produce linear and even super-linear speedups on a number of relevant DSP kernels and applications

Ultrasound ceramic transducer arrays : control, transmission and reception circuits

Orientador: Eduardo Tavares CostaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Os equipamentos de imagem por ultra-som associam diferentes técnicas e provêm informações não só das estruturas anatômicas como também do estado funcional dos diversos sistemas, em tempo real, com excelente qualidade de imagem. Isto se deve ao desenvolvimento de transdutores cada vez mais aprimorados e, ainda, da utilização de eletrônica digital, analógica e mista com microprocessadores, processadores digitais de sinais (DSPs - digital signal processors) e lógica programável (FPGAs - field programmable gate arrays) cada vez mais rápidos e potentes, aliados à utilização de novas técnicas de processamento digital de sinais e de imagens. O presente trabalho teve como objetivo o desenvolvimento de circuitos de acionamento de elementos cerâmicos de transdutores matriciais. Estes circuitos são responsáveis pela geração e recepção de ondas ultra-sônicas e foram desenvolvidos utilizando técnicas de projetos específicos de placas de circuito impresso de alta freqüência e multicamadas. Foram utilizados componentes SMD (surface-mounted devices) para redução do tamanho do hardware. O sistema é formado por um circuito de controle, uma placa de interligação, uma fonte de alimentação com 10 níveis de tensão, e duas placas de circuito impresso (PCI) contendo os circuitos de transmissão e de recepção (4 canais) para transdutores de ultra-som matriciais. No circuito de controle foi utilizada a linguagem de descrição de hardware VHDL. Este circuito de controle é capaz de executar a variação de largura de pulso, taxa de repetição e defasagem de acionamento dos elementos do transdutor matricial para focalização e deflexão do feixe acústico. Os circuitos de transmissão geram pulsos de até +65V e são disparados pelos pulsos digitais do circuito de controle (mínimo de 20ns de largura). Os circuitos de proteção são eficientes atenuando os pulsos de alta tensão na entrada do circuito de recepção e permitindo a passagem dos ecos. Os circuitos de recepção são formados por circuitos integrados de tecnologia mista (analógico e digital) com faixa de passagem de 100 MHz, baixo ruído e ganho máximo de 70dB. Este ganho pode ser configurado através dos três estágios de amplificação independentes do componente utilizado (LNA, VCA e PGA). O sistema foi testado em laboratório e apresentou desempenho adequado, mostrando-se versátil, permitindo seu uso com transdutores matriciais e mostrando-se interessante ferramenta para laboratórios de ensino e pesquisa em ultra-som.Abstract: Ultrasound image equipments associate different techniques to provide not only anatomical but also functional information of body parts and organs in real time and with excellent image quality. This is due to great advances in transducer technology and also to digital and analog electronics with the use of microcomputers, digital signal processors (DSPs) and field programmable gate arrays (FPGAs) even faster and powerful, allied to new digital signal and image processing techniques. The objective of the present work was the development and construction of circuits to actuate on piezoelectric ceramic transducer arrays. The circuits are able to generate and receive ultrasound waves and were developed with techniques for high frequency multilayer printed circuit boards. In order to reduce hardware size it was used surface mounted devices (SMD). The system consists of a control circuit, a interconnection board, power supply (10 different voltage), two four channel printed circuit boards with the transmission and reception circuits to be used with transducer arrays. It was used VHDL for hardware description language and the control circuit defines pulse width, repetition rate and temporal phasing for activation of each element of the transducer array enabling focusing and ultrasound beam in different directions. The transmission circuits generate pulses up to +65V that are triggered by the control circuit (20 ns minimum pulse width). The protection circuit is very efficient avoiding high tension electrical surges. The reception circuits have mixed technologies (analog and digital integrated circuits) with 100 MHz bandwidth , low noise and up to 70 dB gain. This gain can be programmed through 3 independent amplification stages (LNA, VCA and PGA). The system has been tested in laboratory and presented adequate performance, being versatile and allowing its use with array transducers becoming an interesting tool for education and research purposes.MestradoEngenharia BiomedicaMestre em Engenharia Elétric

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

Theory and Practice of Cryptography and Network Security Protocols and Technologies

In an age of explosive worldwide growth of electronic data storage and communications, effective protection of information has become a critical requirement. When used in coordination with other tools for ensuring information security, cryptography in all of its applications, including data confidentiality, data integrity, and user authentication, is a most powerful tool for protecting information. This book presents a collection of research work in the field of cryptography. It discusses some of the critical challenges that are being faced by the current computing world and also describes some mechanisms to defend against these challenges. It is a valuable source of knowledge for researchers, engineers, graduate and doctoral students working in the field of cryptography. It will also be useful for faculty members of graduate schools and universities

Instruction cache optimizations for embedded systems

Ph.DDOCTOR OF PHILOSOPH

HYPERSPECTRAL IMAGING AND PATTERN RECOGNITION TECHNOLOGIES FOR REAL TIME FRUIT SAFETY AND QUALITY INSPECTION

Hyperspectral band selection and band combination has become a powerful tool and have gained enormous interest among researchers. An important task in hyperspectral data processing is to reduce the redundancy of the spectral and spatial information without losing any valuable details that are needed for the subsequent detection, discrimination and classification processes. An integrated principal component analysis (PCA) and Fisher linear discriminant (FLD) method has been developed for feature band selection, and other pattern recognition technologies have been applied and compared with the developed method. The results on different types of defects from cucumber and apple samples show that the integrated PCA-FLD method outperforms PCA, FLD and canonical discriminant methods when they are used separately for classification. The integrated method adds a new tool for the multivariate analysis of hyperspectral images and can be extended to other hyperspectral imaging applications. Dimensionality reduction not only serves as the first step of data processing that leads to a significant decrease in computational complexity in the successive procedures, but also a research tool for determining optimal spectra requirement for online automatic inspection of fruit. In this study, the hyperspectral research shows that the near infrared spectrum at 753nm is best for detecting apple defect. When applied for online apple defect inspection, over 98% of good apple detection rate is achieved. However, commercially available apple sorting and inspection machines cannot effectively solve the stem-calyx problems involved in automatic apple defects detection. In this study, a dual-spectrum NIR/MIR sensing method is applied. This technique can effectively distinguish true defects from stems and calyxes, which leads to a potential solution of the problem. The results of this study will advance the technology in fruit safety and quality inspection and improve the cost-effectiveness of fruit packing processes

System-level power management using online machine learning for prediction and adaptation

Nowadays embedded devices have the need to be portable, battery powered and high performance. This need for high performance makes power management a matter of critical priority. Power management algorithms exist, but most of the approaches focus on an energy-performance trade-off oblivious to the applications running on the system. Others are application-specific and their solution cannot be applied to other applications.This work proposes Shepherd, a cross-layer runtime management system for reduction of energy consumption whilst offering soft real-time performance. It is cross-layer because it takes the performance requirements from the application, and learns to adjust the power management knobs to provide the expected performance at the minimum cost of energy. Shepherd is implemented as a Linux governor running at OS level, this layer offers a low-overhead interface to change the CPU voltage and frequency dynamically.As opposed to the reactive behaviour of Linux Governors, Shepherd adapts to the application-specific performance requirements dynamically, and proactively selects the power state that fulfils these requirements while consuming the least power. Proactiveness is achieved by using AEWMA for adapting to the upcoming workload. These adaptations are facilitated using a model-free reinforcement learning algorithm, that once it learns the optimal decisions it starts exploiting them. This work enables Shepherd to work with different applications. A programming framework was designed to allow programmers to develop their applications to be power-aware, by enabling them to send their performance requirements and annotations to Shepherd and provide the cross-layer soft real-time performance desired.Shepherd is implemented within the Linux Kernel 3.7.10, interfacing with the application and hardware to select an appropriate voltage-frequency control for the executing application. The performance of Shepherd is demonstrated on an ARM Cortex-A8 processor. Experiments conducted with multimedia applications demonstrate that Shepherd minimises energy consumption by up to 30% against existing Governors. Also, the framework has been used to adapt example applications to work with Shepherd, achieving 60% energy savings compared to the existing approaches