Simulation and Optimisation of SiGe MOSFETs

This research project is concerned with the development of methodology for simulating advanced SiGe MOSFETs using commercial simulators, the calibration of simulators against higher level Monte Carlo simulation results and real device measurements, and the application of simulation tools in the design of next generation p- channel devices. The methodology for the modelling and simulation of SiGe MOSFET devices is outlined. There are many simulation approaches widely used to simulate SiGe devices, such as Monte Carlo, hydrodynamic, energy transport, and drift diffusion. Different numerical techniques including finite difference, finite box and finite element methods, may be used in the simulators. The Si0.8Ge0.2 p-MOSFETs fabricated especially for high-field transport studies and the Si0.64Ge0.36 p-channel MOSFETs fabricated at Warwick and Southampton Universities with a CMOS compatible process in varying gate lengths were calibrated and investigated. Enhanced low field mobility in SiGe layers compared to Si control devices was observed. The results indicated that the potential of velocity overshoot effects for SiGe p-MOSFETs was considerably higher than Si counterparts, promising higher performance in the former at equal gate lengths at ultra-small devices. The effects of punchthrough stopper, undoped buffers and delta doping for SiGe p-MOSFETs were analysed systematically. It was found that the threshold voltage roll off might be reduced considerably by using an appropriate punchthrough stopper. In order to adjust the threshold voltage for digital CMOS applications, p-type delta doping was required for n+-polysilicon gate p-MOSFET. The use of delta doping made the threshold voltage roll off a more serious issue, therefore delta doping should be used with caution. The two-dimensional process simulator TSUPREM-4 and the two-dimensional device simulator MEDICI were employed to optimise and design Si/SiGe hybrid CMOS. The output of TSUPREM-4 was transferred automatically to the MEDICI device simulator. This made the simulation results more realistic. For devices at small gate length, lightly doped drain (LDD) structures were required. They would decrease the lateral subdiffusion and allow threshold voltage roll off to be minimised. These structures, however, would generally reduce drain current due to an increase in the series resistance of the drain region. Further consideration must be made of these trade-offs. Comparison between drift diffusion and hydrodynamic simulation results for SiGe p-MOSFETs were presented for the first time, with transport parameters extracted from our in-house full-band hole Monte Carlo transport simulator. It was shown that while drift diffusion and hydrodynamic simulations provided a reasonable estimation of the I-V characteristics for Si devices, the same could not be said for aggressively scaled SiGe devices. The resulting high fields at the source end of the devices meant that nonequilibrium transport effects were significant. Therefore for holes, models based on an isotropic carrier temperature were no longer appropriate, as it was shown by analysing the tensor components of the carrier temperature obtained from Monte Carlo simulation. Two-dimensional drift diffusion and Monte Carlo simulations of well-tempered Si p-MOSFETs with gate lengths of 25 and 50 nm were performed. By comparing Monte Carlo simulations with carefully calibrated drift diffusion results, it was found that nonequilibrium transport was important for understanding the high current device characteristics in sub 0.1 mum p-MOSFETs. The well-tempered devices showed better characteristics than the conventional SiGe devices. Both threshold voltage roll off and the subthreshold slope were acceptable although the effective channel length of this device was reduced from 50 nm to 25 nm. In order to adjust the threshold voltage for the digital CMOS applications, p-type delta doping was used for 50 nm well-tempered SiGe p- MOSFETs. As the delta doping made the threshold voltage roll off too serious, it was not suitable for 25 nm well-tempered SiGe p-MOSFETs

Quantum corrected full-band semiclassical Monte Carlo simulation research of charge transport in Si, stressed-Si, and SiGe MOSFETs

This Ph.D. research is centered around a full-band Monte Carlo device simulator (“Monte Carlo at the University of Texas”, MCUT) with quantum corrections (based on one-dimensional Schrödinger equation solver). The code itself was based on a solid infrastructure of a Monte Carlo simulator, “MoCa” from the University of Illinois at Urbana-Champaign. To that there were added new methods and features during my Ph.D. program, including strained band structures, alternative (to conventional 100 ) surface orientations, full-band scattering mechanisms, and valley-dependent quantum correction. These features enable “MCUT” to be used to model various strained and/or alloyed silicon MOSFETs, as well as the MOSFETs composed of alternative materials such as Ge, in sub-100 nm regime. Monte Carlo simulation, itself, handles short channel effects and hot carriers in ultra small device well; full-band structure replaces the inaccurate and unknown (for new/strained materials) analytical formulae; and the quantum corrections approximate quantum-confinement effects on device performance. The goal is to understand and predict the device behavior of the so called “non-classical” CMOS ― beyond bulk Si based CMOS ― in the sub-100 nm regime.Electrical and Computer Engineerin

Investigation of the electrical properties of Si₁-×Ge× channel pMOSFETs with high-κ dielectrics

It is now apparent that the continued performance enhancements of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) can no longer be met by scaling alone. High-mobility channel materials such as strained Si1-xGex and Ge are now being seriously considered to maintain the performance requirements specified by the semiconductor industry. In addition, alternative gate dielectric, or high-κ dielectrics, will also be required to meet gate leakage requirements. This work investigates the properties of using strained Si1-xGex or Ge as alternative channel materials for pMOSFETs incorporating hafnium oxide (HfO2) high-κ gate dielectric. Whilst the SiGe pMOSFETs (x = 0.25) exhibited an enhancement in hole mobility (300 K) over comparable silicon control pMOSFETs with sputtered HfO2 dielectric, high Coulomb scattering and surface roughness scattering relating to the dielectric deposition process meant that the effective hole mobilities were degraded with respect to the silicon universal curve. Germanium channel pMOSFETs with halo-doping and HfO2 gate dielectric deposited by atomic layer deposition showed high hole mobilities of 230 cm2V-1s-1 and 480 cm2V-1s-1 at room temperature and 77 K, respectively. Analysis of the off-state current for the Ge pMOSFETs over a range of temperatures indicated that band-to-band tunnelling, gate-induced drain leakage and other defect-assisted leakage mechanisms could all be important. Hole carrier velocity and impact ionisation were also studied in two batches of buried channel SiGe pMOSFET with x = 0.15 and x = 0.36, respectively. SiGe channel pMOSFETs were found to exhibit reduced impact ionisation compared to silicon control devices, which has been attributed to a strain-induced reduction of the density of states in the SiGe conduction and valence bands. Analysis of the hole carrier velocity indicated that pseudomorphic SiGe offered no performance enhancements over Si below 100 nm, possibly due to higher ion implantation damage and strain relaxation of the strained SiGe channel. The results indicate that velocity overshoot effects might not provide the performance improvements at short channel lengths that was previously hoped for

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Monte Carlo simulation of silicon-germanium transistors

Self-consistent Monte Carlo simulation studies of n-channel Si/SiGe modulation doped field effect transistors (MODFETs) and silicon-on-insulator lateral bipolar junction transistors (SOI- LBJTs) are reported in this thesis. As a preliminary to the device studies Monte Carlo simulations of electron transport in bulk Si strained as if grown on Si(_0.77)Ge(_0.23) and Si(_0.55)Ge(_0.45) substrates have been carried out at 300 K, for field strengths varied from 10(^4) to 2 x 10(^7) Vm(^-1). The calculations indicate an enhancement of the average electron drift velocity when Si is tensilely strained in the growth plane. The enhancement of electron velocity is more marked at low and intermediate electric fields, while at very high fields the velocity saturates at about the same value as unstrained Si. In addition the ensemble Monte Carlo method has been used to study the transient response to a stepped electric field of electrons in strained and unstrained Si. The calculations suggest that significant velocity overshoots occurs in strained material. Simulations of n-channel Si/Si(_1=z)Ge(_z) MODFETs with Ge fractions of 0.23, 0.25, and 0.45 have been performed. Five depletion mode devices with x = 0.23 and 0.25 were studied. The simulations provide information on the microscopic details of carrier behaviour, including carrier velocity, kinetic energy and carrier density, as a function of position in the device. Detailed time-dependent voltage signal analysis has been carried out to test device response and derive the frequency bandwidth. The simulations predict a current gain cut-off frequency of 60 ± 10 GHz for a device with a gate length of 0.07 /nm and a channel length of 0.25 um. Similar studies of depletion and enhancement mode n-channel Si/Sio.55Geo.45 MODFETs with a gate length of 0.18 /im have been carried out. Cut-off frequencies of 60 ±10 GHz and 90± 10 GHz are predicted for the depletion and enhancement mode devices respectively. A Monte Carlo model has also been devised and used to simulate steady state and transient electron and hole transport in SOI-LBJTs. Four devices have been studied and the effects of junction depth and silicon layer thickness have been investigated. The advantage of the silicon-on-insulator technology SOI device is apparent in terms of higher collector current, current gain, and cut-off frequency obtained in comparison with an all-silicon structure. The simulations suggest that the common-emitter current gain of the most promising SOI-LBJT structure considered could have a cut-off frequency approaching 35 ± 5 GHz

Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism