Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Implementation of a 200 MSps 12-bit SAR ADC

Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.Från analogt till digitalt - snabba och strömsnåla omvandlare Dagens digitala samhälle ställer höga krav på prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnås hög hastighet och låg strömförbrukning som ligger i forskningens framkant. Från analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer är så kallade A/D-omvandlare, som översätter mellan analoga signaler (till exempel ljud) och digitala signaler bestående av ettor och nollor. En väldigt effektiv metod för A/D-omvandling bygger på så kallad successiv approximation. Metoden innebär att signalen som ska omvandlas jämförs med en referensnivå, som stegvis justeras för att närma sig signalens värde. Till slut har man en tillräckligt god uppskattning av värdet som ska mätas. Just en sådan omvandlare har utvecklats med höga krav på hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. Referensnivån skapas ofta genom att styra ett nätverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror på hur många nivåer som finns tillgängliga det vill säga hur nära signalens värde man kan komma. I den designade kretsen finns hela 4096 nivåer! Det finns många källor till osäkerhet i systemet, bland annat hur exakta referensnivåerna är och hur bra jämförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försämring av omvandlingens noggrannhet måste alla delar i kretsen utformas med detta i åtanke. Höga hastigheter Eftersom det krävs många steg för referensnivån att närma sig signalens värde är den maximala omvandlingshastigheten ofta begränsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade på successiv approximation kan uppnå hastigheter på flera miljoner mätvärden varje sekund, vilket även den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar när det gäller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nätverket. Genom små ändringar kunde nätverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar är hög medför varje minskning av kretsens area att kostnaden sjunker

Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies

This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics

High speed – energy efficient successive approximation analog to digital converter using tri-level switching

This thesis reports issues and design methods used to achieve high-speed and high-resolution Successive Approximation Register analog to digital converters (SAR ADCs). A major drawback of this technique relates to the mismatch in the binary ratios of capacitors which causes nonlinearity. Another issue is the use of large capacitors due to nonlinear effect of parasitic capacitance. Nonlinear effect of capacitor mismatch is investigated in this thesis. Based on the analysis, a new Tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over conventional SAR ADC, which is the lowest compared to the previously reported schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% compared with the conventional SAR architecture. A new correction method to solve metastability error of comparator based on a novel design approach is proposed which reduces the required settling time about 1.1τ for each conversion cycle. Based on the above proposed methods two SAR ADCs: an 8-bit SAR ADC with 50MS/sec sampling rate, and a 10-bit SAR split ADC with 70 MS/sec sampling rate have been designed in 0.18μm Silterra complementary metal oxide semiconductor (CMOS) technology process which works at 1.2V supply voltage and input voltage of 2.4Vp-p. The 8-bit ADC digitizes 25MHz input signal with 48.16dB signal to noise and distortion ratio (SNDR) and 52.41dB spurious free dynamic range (SFDR) while consuming about 589μW. The figure of merit (FOM) of this ADC is 56.65 fJ/conv-step. The post layout of the 10-bit ADC with 1MHz input frequency produces SNDR, SFDR and effective number of bits (ENOB) of 57.1dB, 64.05dB and 9.17Bit, respectively, while its DNL and INL are -0.9/+2.8 least significant bit (LSB) and -2.5/+2.7 LSB, respectively. The total power consumption, including digital, analog and reference power, is 1.6mW. The FOM is 71.75fJ/conv. step

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Behavior-level Analysis of a Successive Stochastic Approximation Analog-to-Digital Conversion System for Multi-channel Biomedical Data Acquisition

In the present paper, we propose a novel high-resolution analog-to-digital converter (ADC) for low-power biomedical analog frontends, which we call the successive stochastic approximation ADC. The proposed ADC uses a stochastic flash ADC (SF-ADC) to realize a digitally controlled variable-threshold comparator in a successive-approximationregister ADC (SAR-ADC), which can correct errors originating from the internal digital-to-analog converter in the SAR-ADC. For the residual error after SAR-ADC operation, which can be smaller than thermal noise, the SF-ADC uses the statistical characteristics of noise to achieve high resolution. The SF-ADC output for the residual signal is combined with the SAR-ADC output to obtain high-precision output data using the supervised machine learning method

Successive-approximation-register based quantizer design for high-speed delta-sigma modulators

High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Built-in self-test and self-calibration for analog and mixed signal circuits

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. This dissertation introduces two ADC testing algorithms and two ADC built-in self-test circuit implementations to test the ADC integral nonlinearity (INL) and differential nonlinearity (DNL) on-chip. In the first testing algorithm, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) is developed for ADC built-in self-test, which eliminates the need for precision stimulus and reduces the overall test time. In this algorithm, the ADC is tested twice with a nonlinear ramp, instead of using a linear ramp signal. Therefore, the stimulus can be easily generated on-chip in a low-cost way. For the two ramps, there is a constant voltage shift in between. As the input stimulus linearity is completely relaxed, there is no requirement on the waveform of the input stimulus as long as it covers the ADC input range. In the meantime, the high-resolution ADC linearity is modeled with segmented parameters, which reduces the number of samples required for achieving high-precision test, thus saving the test time. As a result, the USER-SMILE algorithm is able to use less than 1 sample/code nonlinear stimulus to test high resolution ADCs with less than 0.5 least significant bit (LSB) INL estimation error, achieving more than 10-time test time reduction. This algorithm is validated with both board-level implementation and on-chip silicon implementation. The second testing algorithm is proposed to test the INL/DNL for multi-bit-per-stages pipelined ADCs with reduced test time and better test coverage. Due to the redundancy characteristics of multi-bit-per-stages pipelined ADC, the conventional histogram test cannot estimate and calibrate the static linearity accurately. The proposed method models the pipelined ADC nonlinearity as segmented parameters with inter-stage gain errors using the raw codes instead of the final output codes. During the test phase, a pure sine wave is sent to the ADC as the input and the model parameters are estimated from the output data with the system identification method. The modeled errors are then removed from the digital output codes during the calibration phase. A high-speed 12-bit pipelined ADC is tested and calibrated with the proposed method. With only 4000 samples, the 12-bit ADC is accurately tested and calibrated to achieve less than 1 LSB INL. The ADC effective number of bits (ENOB) is improved from 9.7 bits to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by more than 20dB after calibration. In the first circuit implementation, a low-cost on-chip built-in self-test solution is developed using an R2R digital-to-analog converter (DAC) structure as the signal generator and the voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by mismatches, which relaxes the DAC matching requirements and reduces the design area. The R2R DAC based BIST circuit is fabricated in TSMC 40nm technology with a small area of 0.02mm^2. Measurement results show that the BIST circuit is capable of testing a 15-bit ADC INL accurately with less than 0.5 LSB INL estimation error. In the second circuit implementation, a complete SAR ADC built-in self-test solution using the USER-SMILE is developed and implemented in a 28nm automotive microcontroller. A low-cost 12-bit resistive DAC with less than 12-bit linearity is used as the signal generator to test and calibrate a SAR ADC with a target linearity of 12 bits. The voltage shift generation is created inside the ADC with capacitor switching. The entire algorithm processing unit for USER-SMILE algorithm is also implemented on chip. The final testing results are saved in the memory for further digital calibration. Both the total harmonic distortion (THD) and the SFDR are improved by 20dB after calibration, achieving -84.5dB and 86.5dB respectively. More than 700 parts are tested to verify the robustness of the BIST solution