A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorporated into the design using a tri-level switching scheme and our modified split-capacitor array to achieve the highest switching efficiency while still preserving the symmetry in error tolerance. A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed. The calibration is performed by using the input signal as stimulus and the effectiveness is verified both in simulation and through measured data. The prototype achieves a 67.4dB SNDR at 50MS/s, while dissipating 2.1mW from a 1.2V supply, leading to FoM of 21.9fJ/conv.-step at Nyquist frequency.MIT Masdar Progra

캐패시터 미스매치 분석에 기반한 12-bit 1 MSps SAR ADC 설계

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 김수환.본 논문에서는 캐패시터 미스매치가 successive approximation register (SAR) analog-to-digital converter (ADC)에 미치는 영향을 분석하고 이를 기반으로 설계한 캐패시터 digital-to-analog converter (DAC)으로 구현된 SAR ADC를 제안한다. 캐패시터 미스매치는 캐패시터 면적의 제곱근에 반비례한다. 따라서 캐패시터 미스매치를 줄이기 위해서는 캐패시터 면적을 늘려야하고 이는 전력 소모를 증가시킨다. 이 때문에 캐패시터 DAC의 크기를 결정하는 것은 SAR ADC의 설계에 있어 매우 중요하며 분석을 통해 최적화된 값을 찾는 것이 중요하다. 본 논문에서는 캐패시터 DAC의 각 캐패시터들의 미스매치로 인한 differential non-linearity (DNL)이 보다 작아지는 최소 캐패시터의 크기를 계산하였으며 이를 기반으로 스플릿 캐패시터 DAC과 더블 스플릿 캐패시터 DAC의 미스매치를 분석하였다. 본 논문은 미스매치 분석을 기반으로 미스매치 성능이 좋지 않은 캐패시터들의 크기를 키워 최적화한 캐패시터 DAC을 제안한다. 브릿지 캐패시터로 인한 선형성 저하를 막기 위해 브릿지 캐패시터 calibration 회로를 추가하였으며, 제안된 캐패시터 DAC의 성능이 기존의 스플릿 캐패시터 DAC의 성능과 비교하였을 때, 향상되었음을 monte carlo 모의실험 결과를 통해 증명하였다. 제안된 1MHz 12-bit SAR ADC 회로는 0.18 µm CMOS 공정에서 구현되었으며, 기준 전압을 내부에서 직접 생성하였다. Nyquist 입력을 주입하였을 때, 11.31 effective number of bits (ENOB)의 결과를 모의실험을 통해 얻었으며 4.6 V의 아날로그 공급 전압과 1.8 V의 디지털 공급전압에서 1.14 mW의 전력을 소모한다.This paper analyzes the impact of capacitor mismatch on successive approximation register analog-to-digital converter and proposes SAR ADC with capacitor digital-to-analog converter based on analysis of capacitor mismatch. The capacitor mismatch is inversely proportional to the square root of the capacitor area. In order to reduce the capacitor mismatch, the capacitor area must be increased, which increases the power consumption. Therefore, determining the size of the capacitor DAC is very important for the SAR ADC design and it is important to find the optimized value through analysis. This paper calculates the minimum capacitor size that the DNL due to the mismatch of each capacitor in the capacitor DAC is less than . Based on mismatch calculation, this paper analyzes the mismatch of both the split capacitor DAC and the double split capacitor DAC. This paper proposes an optimized capacitor DAC based on mismatch analysis by improving the size of capacitors with poor mismatch performance. A bridge capacitor calibration circuit was added to prevent linearity degradation due to the bridge capacitor. Montecarlo simulation results show that the performance of the proposed capacitor DAC is improved when compared with that of the conventional split capacitor DAC. The proposed 1 MHz 12-bit SAR ADC circuit is implemented in a 0.18 µm CMOS process and the reference voltage is directly generated internally. When the Nyquist input is injected, the result of 11.31 ENOB is obtained through simulation and consumes 1.14 mW of power at an analog supply voltage of 4.6 V and a digital supply voltage of 1.8 V.제 1 장 서 론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 SAR ADC의 동작 원리 4 제 2 장 캐패시터 DAC 8 제 1 절 캐패시터 DAC의 design issues 8 1. kT/C 잡음 8 2. 안정화 시간 10 3. 캐패시터 미스매치 11 제 2 절 스플릿 캐패시터 DAC 13 제 3 절 브릿지 캐패시터 미스매치 calibration 기법 16 1. 브릿지 캐패시터 미스매치 calibration 기법의 원리 16 2. 브릿지 캐패시터 미스매치 calibration 기법의 동작 설명 21 제 3 장 제안하는 캐패시터 DAC을 이용한 SAR ADC의 설계 24 제 1 절 캐패시터 DAC 미스매치 분석 24 1. 캐패시터 미스매치 계산 24 2. 스플릿 캐패시터 DAC의 미스매치 분석 26 3. 더블 스플릿 캐패시터 DAC의 미스매치 분석 27 제 2 절 제안하는 캐패시터 DAC 29 제 3 절 SAR ADC의 구현 31 제 4 장 Layout 및 모의실험 결과 36 제 1 절 Layout 36 제 2 절 모의실험 결과 37 제 5 장 결 론 43 참고문헌 44 Abstract 45Maste

A Three-Step Resolution-Reconfigurable Hazardous Multi-Gas Sensor Interface for Wireless Air-Quality Monitoring Applications

This paper presents a resolution-reconfigurable wide-range resistive sensor readout interface for wireless multi-gas monitoring applications that displays results on a smartphone. Three types of sensing resolutions were selected to minimize processing power consumption, and a dual-mode front-end structure was proposed to support the detection of a variety of hazardous gases with wide range of characteristic resistance. The readout integrated circuit (ROIC) was fabricated in a 0.18 ??m CMOS process to provide three reconfigurable data conversions that correspond to a low-power resistance-to-digital converter (RDC), a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a 16-bit delta-sigma modulator. For functional feasibility, a wireless sensor system prototype that included in-house microelectromechanical (MEMS) sensing devices and commercial device products was manufactured and experimentally verified to detect a variety of hazardous gases

8-bit 50ksps ULV SAR ADC

With the growing market of MCUs and embedded electronic powered by batteries, more energy efficient peripherals are needed. This project presents an Analog to Digital converter using ultra low supply voltage on transistor level. With a charge recycling spilt capacitive DAC using set and down switching method. And a comparator with a dynamic amplifier, resulted in a very energy efficient SAR ADC. The ADC got a samplings rate of 50k Hz and an ENOB of 7.89 bits, while only draining 75nW power from a 0.5V supply. This results in a Walden FOM of 7.39fJ/conv.step

High speed – energy efficient successive approximation analog to digital converter using tri-level switching

This thesis reports issues and design methods used to achieve high-speed and high-resolution Successive Approximation Register analog to digital converters (SAR ADCs). A major drawback of this technique relates to the mismatch in the binary ratios of capacitors which causes nonlinearity. Another issue is the use of large capacitors due to nonlinear effect of parasitic capacitance. Nonlinear effect of capacitor mismatch is investigated in this thesis. Based on the analysis, a new Tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over conventional SAR ADC, which is the lowest compared to the previously reported schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% compared with the conventional SAR architecture. A new correction method to solve metastability error of comparator based on a novel design approach is proposed which reduces the required settling time about 1.1τ for each conversion cycle. Based on the above proposed methods two SAR ADCs: an 8-bit SAR ADC with 50MS/sec sampling rate, and a 10-bit SAR split ADC with 70 MS/sec sampling rate have been designed in 0.18μm Silterra complementary metal oxide semiconductor (CMOS) technology process which works at 1.2V supply voltage and input voltage of 2.4Vp-p. The 8-bit ADC digitizes 25MHz input signal with 48.16dB signal to noise and distortion ratio (SNDR) and 52.41dB spurious free dynamic range (SFDR) while consuming about 589μW. The figure of merit (FOM) of this ADC is 56.65 fJ/conv-step. The post layout of the 10-bit ADC with 1MHz input frequency produces SNDR, SFDR and effective number of bits (ENOB) of 57.1dB, 64.05dB and 9.17Bit, respectively, while its DNL and INL are -0.9/+2.8 least significant bit (LSB) and -2.5/+2.7 LSB, respectively. The total power consumption, including digital, analog and reference power, is 1.6mW. The FOM is 71.75fJ/conv. step

Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s

The work in this thesis is based on the investigation and design of key circuit blocks in a high speed, high resolution SAR ADC in TSMC’s 28nm technology. The research carried out analyses the circuit limitations of the switched capacitor DAC and the settling problems of the reference voltage associated with a switched capacitor scheme. The switched capacitor DAC is a critical block for overall ADC performance and various trade-offs are weighed up before discussing the layout of the split capacitor DAC implemented in the project, from unit capacitor up to top level routing. It also investigates the main sources of error using this topology and implements effective ways of mitigating these errors. The schematic design of DAC switches is also carried out and the results section discusses the top level linearity performance of the DAC. This work also focuses on detailed analysis and implementation of a reference buffer circuit solution that is capable of supplying a reference voltage that is highly accurate and can settle in enough time for the high speed and high resolution specifications required by the SAR ADC. Various solutions were comprehensively investigated for this problem and the design of the chosen flipped voltage follower topology was implemented in schematic and layout. It was subsequently simulated at schematic and extracted parasitics level to verify its functionality and determine its overall performance. Finally, the work done in each block is verified in the context of the whole ADC by top level schematic and extracted layout simulation

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Department of Electrical EngineeringA Sensor system is advanced along sensor technologies are developed. The performance improvement of sensor system can be expected by using the internet of things (IoT) communication technology and artificial neural network (ANN) for data processing and computation. Sensors or systems exchanged the data through this wireless connectivity, and various systems and applications are possible to implement by utilizing the advanced technologies. And the collected data is computed using by the ANN and the efficiency of system can be also improved. Gas monitoring system is widely need from the daily life to hazardous workplace. Harmful gas can cause a respiratory disease and some gas include cancer-causing component. Even though it may cause dangerous situation due to explosion. There are various kinds of hazardous gas and its characteristics that effect on human body are different each gas. The optimal design of gas monitoring system is necessary due to each gas has different criteria such as the permissible concentration and exposure time. Therefore, in this thesis, conventional sensor system configuration, operation, and limitation are described and gas monitoring system with wireless connectivity and neural network is proposed to improve the overall efficiency. As I already mentioned above, dangerous concentration and permissible exposure time are different depending on gas types. During the gas monitoring, gas concentration is lower than a permissible level in most of case. Thus, the gas monitoring is enough with low resolution for saving the power consumption in this situation. When detecting the gas, the high-resolution is required for the accurate concentration detecting. If the gas type is varied in the above situation, the amount of calculation increases exponentially. Therefore, in the conventional systems, target specifications are decided by the highest requirement in the whole situation, and it occurs increasing the cost and complexity of readout integrated circuit (ROIC) and system. In order to optimize the specification, the ANN and adaptive ROIC are utilized to compute the complex situation and huge data processing. Thus, gas monitoring system with learning-based algorithm is proposed to improve its efficiency. In order to optimize the operation depending on situation, dual-mode ROIC that monitoring mode and precision mode is implemented. If the present gas concentration is decided to safe, monitoring mode is operated with minimal detecting accuracy for saving the power consumption. The precision mode is switched when the high-resolution or hazardous situation are detected. The additional calibration circuits are necessary for the high-resolution implementation, and it has more power consumption and design complexity. A high-resolution Analog-to-digital converter (ADC) is kind of challenges to design with efficiency way. Therefore, in order to reduce the effective resolution of ADC and power consumption, zooming correlated double sampling (CDS) circuit and prediction successive approximation register (SAR) ADC are proposed for performance optimization into precision mode. A Microelectromechanical systems (MEMS) based gas sensor has high-integration and high sensitivity, but the calibration is needed to improve its low selectivity. Conventionally, principle component analysis (PCA) is used to classify the gas types, but this method has lower accuracy in some case and hard to verify in real-time. Alternatively, ANN is powerful algorithm to accurate sensing through collecting the data and training procedure and it can be verified the gas type and concentration in real-time. ROIC was fabricated in complementary metal-oxide-semiconductor (CMOS) 180-nm process and then the efficiency of the system with adaptive ROIC and ANN algorithm was experimentally verified into gas monitoring system prototype. Also, Bluetooth supports wireless connectivity to PC and mobile and pattern recognition and prediction code for SAR ADC is performed in MATLAB. Real-time gas information is monitored by Android-based application in smartphone. The dual-mode operation, optimization of performance and prediction code are adjusted with microcontroller unit (MCU). Monitoring mode is improved by x2.6 of figure-of-merits (FoM) that compared with previous resistive interface.clos

축차 비교형 아날로그-디지털 변환기의 성능 향상을 위한 기법에 대한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 김수환.This thesis is written about a performance enhancement technique for the successive-approximation-register analog-to-digital converter (SAR ADC). More specifically, it focuses on improving the resolution of the SAR ADC. The basic operation principles and the architecture of the conventional SAR ADC is examined. To gain insight on areas of improvement, a deeper look is taken at the building components of the SAR ADC. Design considerations of these components are discussed, along with the performance limiting factors in the resolution and bandwidth domains. Prior works which challenge these problems in order to improve the performance of the SAR ADC are presented. To design SAR ADCs, a high-level modeling is presented. This model includes various non-ideal effects that occur in the design and operation. Simulation examples are shown how the model is efficient and useful in the initial top-level designing of the SAR ADC. Then, the thesis proposes a technique that can enhance the resolution. The SAR ADC using integer-based capacitor digital-to-analog converter (CDAC) exploiting redundancy is presented. This technique improves the mismatch problem that arises with the widely used split-capacitor structure in the CDAC of the SAR ADC. Unlike prior works, there is no additional overhead of additional calibration circuits or reference voltages. A prototype SAR ADC which uses the integer-based CDAC exploiting redundancy is designed for automotive applications. Measurement results show a resolution level of 12 bits even without any form of calibration. Finally, the conclusion about the operation and effectiveness on the proposed technique is drawn.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 7 2.1 INTRODUCTION 7 2.2 OPERATION PRINCIPLE OF THE CONVENTIONAL SAR ADC 8 2.2.1. OVERVIEW OF THE OPERATION 8 2.2.2. SAMPLING PHASE 10 2.2.3. CONVERSION PHASE 11 2.3 STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.1. FULL STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.2. CAPACITOR DIGITAL-TO-ANALOG CONVERTER (CDAC) 17 2.3.3. COMPARATOR 21 2.3.4. CONTROL LOGIC 23 2.4 PERFORMANCE LIMITING FACTORS 24 2.4.1. RESOLUTION LIMITING FACTORS 24 2.4.2. OPERATION BANDWIDTH LIMITING FACTORS 28 2.5 PRIOR WORK 30 2.5.1. INTRODUCTION 30 2.5.2. SPLIT-CAPACITOR STRUCTURE OF THE CDAC 31 2.5.3. REDUNDANCY AND CDAC WEIGHT DISTRIBUTION 33 2.5.4. ASYNCHRONOUS CONTROL LOGIC 36 2.5.5. CALIBRATION TECHNIQUES 37 2.5.4. DOUBLE-SAMPLING TECHNIQUE FOR SAMPLING TIME REDUCTION 38 2.5.6. TWO-COMPARATOR ARCHITECTURE FOR COMPARATOR DECISION TIME REDUCTION 40 2.5.7. MAJORITY VOTING FOR RESOLUTION ENHANCEMENT 41 CHAPTER 3 MODELING OF THE SAR ADC 43 3.1 INTRODUCTION 43 3.2 WEIGHT DISTRIBUTION OF THE CAPACITOR DAC AND REDUNDANCY 44 3.3 SPLIT-CAPACITOR ARRAY TECHNIQUE 47 3.4 PARASITIC EFFECTS OF THE CAPACITOR DAC 48 3.5 MISMATCH MODEL OF THE CAPACITOR DAC 51 3.6 SETTLING ERROR OF THE DAC 53 3.7 COMPARATOR DECISION ERROR 58 3.8 DIGITAL ERROR CORRECTION 59 CHAPTER 4 SAR ADC WITH INTEGER-BASED SPLIT-CDAC EXPLOITING REDUNDANCY FOR AUTOMOTIVE APPLICATIONS 60 4.1 INTRODUCTION 60 4.2 MOTIVATION 61 4.3 PRIOR WORK ON RESOLVING THE SPLIT-CAPACITOR CDAC MISMATCH FOR THE SAR ADC 64 4.3.1. CONVENTIONAL SPLIT-CAPACITOR CDAC FOR THE SAR ADC 64 4.3.2. SPLITTING THE LAST STAGE OF THE LSB-SIDE OF THE CDAC 66 4.3.3. CALIBRATION OF THE NON-INTEGER MULTIPLE BRIDGE CAPACITOR 67 4.3.4. INTEGER-MULTIPLE BRIDGE CAPACITOR WITH LSB-SIDE CAPACITOR ARRAY CALIBRATION 68 4.3.5. OVERSIZED BRIDGE CAPACITOR WITH ADDITIONAL FRACTIONAL REFERENCE VOLTAGE 69 4.4 PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR THE SAR ADC 70 4.5 CIRCUIT DESIGN 72 4.5.1. PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR SAR ADC 72 4.5.2. COMPARATOR 74 4.5.3. CONTROL LOGIC 75 4.6 IMPLEMENTATION AND EXPERIMENTAL RESULTS 76 4.6.1. LAYOUT 76 4.6.2. MEASUREMENT RESULTS AND CONCLUSIONS 82 CHAPTER 5 CONCLUSION AND FUTURE WORK 86 5.1 CONCLUSION 86 5.2 FUTURE WORK 87 APPENDIX. SAR ADC USING THRESHOLD-CONFIGURING COMPARATOR FOR ULTRASOUND IMAGING SYSTEMS 89 BIBLIOGRAPHY 120Docto

Noise-Shaping SAR ADCs.

This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping converters. Because charge-redistribution SAR ADCs contain few active components and rely on highly digital controllers, SAR ADCs demonstrate the best energy efficiencies of all low bandwidth, moderate resolution converters (~10 bits). SAR ADCs achieve remarkable power efficiency at low resolution, but as the resolution of the SAR ADC increases, the specifications for input-referred comparator noise become more stringent and total DAC capacitance becomes too large, which degrades both power efficiency and bandwidth. For these reasons, lower resolution, lower bandwidth applications tend to favor traditional SAR ADC architectures, while higher bandwidth, higher resolution applications tend to favor pipeline-SARs. Although the use of amplifiers in pipeline-assisted SARs relaxes the comparator noise requirements and improves bandwidth, amplifier design becomes more of a challenge in highly scaled processes with reduced supply voltages. In this work, we explore the use of feedback and noise-shaping to enhance the resolution of SAR ADCs. Unlike pipeline-SARs, which require high-gain, linear amplifiers, noise-shaping SARs can be constructed using passive FIR filter structures. Furthermore, the use of feedback and noise-shaping reduces the impact of thermal kT/C noise and comparator noise. This work details and explores a new class of noise-shaping SARs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/113647/1/fredenbu_1.pd