A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorporated into the design using a tri-level switching scheme and our modified split-capacitor array to achieve the highest switching efficiency while still preserving the symmetry in error tolerance. A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed. The calibration is performed by using the input signal as stimulus and the effectiveness is verified both in simulation and through measured data. The prototype achieves a 67.4dB SNDR at 50MS/s, while dissipating 2.1mW from a 1.2V supply, leading to FoM of 21.9fJ/conv.-step at Nyquist frequency.MIT Masdar Progra

Boning, Duane S.

Chang, Albert H.

Lee, Hae-Seung

Albert H. Chang

Hae-Seung Lee

Duane Boning

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A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

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A 12b 50MS/s 2.1mW SAR ADC with Redundancyand Digital Background CalibrationAlbert H. Chang, Hae-Seung Lee and Duane BoningMicrosystems Technology Laboratories, MIT, Cambridge, MAEmails: ahchang@mit.edu, hslee@mtl.mit.edu and boning@mtl.mit.eduAbstract— A 12-bit 50MS/s SAR ADC implemented in 65nmCMOS technology is presented. The design employs redundancyto relax the DAC settling requirement and to provide sufficientroom for errors such that the static nonlinearity caused bycapacitor mismatches can be digitally removed. The redundancyis incorporated into the design using a tri-level switching schemeand our modified split-capacitor array to achieve the highestswitching efficiency while still preserving the symmetry in errortolerance. A new code-density based digital background calibra-tion algorithm that requires no special calibration signals oradditional analog hardware is also developed. The calibrationis performed by using the input signal as stimulus and theeffectiveness is verified both in simulation and through measureddata. The prototype achieves a 67.4dB SNDR at 50MS/s, whiledissipating 2.1mW from a 1.2V supply, leading to FoM of21.9fJ/conv.-step at Nyquist frequency.I. INTRODUCTIONThere is a growing demand for low-power, high-speedand high-resolution A/D converters for applications suchas wideband wired/wireless communication, software radioand millimeter-wave imaging systems. For many years, thesuccessive-approximation-register (SAR) ADC mostly appearsin low-speed and low-power applications. The unprecedentedimprovement in speed and energy efficiency of scaled CMOStechnologies helps expand the SAR architecture into themedium-to-high-speed application domains that are tradition-ally designed using the flash or pipelined architectures. Alongwith other benefits, such as good digital compatibility, excel-lent power and area efficiency, and rail-to-rail input swings,the SAR architecture has become one of the more populartopologies.Recent SAR designs have demonstrated outstanding band-width (running at hundreds of MS/s to GS/s range) andsuperior energy efficiency (with FoM < 100fJ/conv.-step), butthe resolution is limited to less than 10b ENOB. While scalingbenefits speed and power efficiency, it does not improvecapacitor matching and the reduced supply headroom makesdesigning high-resolution ADCs more difficult. Moreover,reference voltage settling also places stringent settling require-ments that limit the maximum operating speed. In this work,redundancy and calibration are introduced in the design to helpalleviate the settling and the mismatch problems. A sub-radix-2 SAR ADC is presented here with several new contributions.First, we incorporate tri-level based switching [1] into a newsplit capacitor architecture to achieve higher energy efficiency.Second, we introduce a new method to implement redundancyࡸ ࡯࡮ ൌ ૛ࡸ ૛ࡸ െ ૚ൗ ࡯4 (16/15)C5 (32/31)C6 (64/63)CVL+/‐ goes out of supply railsࡸ ࡯ࢄ࡯࡮ࢄ ൌ૛ࡸ૛ࡸ െ ૚൅࡯ࢄ૛ࡸ െ ૚࡯4 14 2C5 30 2C6 62 2CVL+/‐ stays within supply rails+‐…………CBVL+VL‐ VM‐ VM+CB૚࡯ ૚࡯ ૛࡯ ૛ࡸି૚࡯ ૚࡯ ૛࡯ ૛ࡹି૚࡯૚࡯ ૚࡯ ૛࡯ ૛ࡸି૚࡯ ૚࡯ ૛࡯ ૛ࡹି૚࡯CX+‐…………CBXVL+VL‐ VM‐ VM+CBXCX૚࡯ ૚࡯ ૛࡯ ૛ࡸି૚࡯ ૚࡯ ૛࡯ ૛ࡹି૚࡯૚࡯ ૚࡯ ૛࡯ ૛ࡸି૚࡯ ૚࡯ ૛࡯ ૛ࡹି૚࡯Fig. 1. Split-capacitor architecture.directly into the SAR ADC with symmetric error-tolerancewindows without increasing design complexity and area over-head. Third, a new code-density based background calibrationalgorithm is developed for this architecture to calibrate againstcapacitor mismatches.II. ADC ARCHITECTURE AND IMPLEMENTATIONA. Split Capacitor ArchitectureIn a SAR design, the input loading and the area/layoutcomplexity of the DAC increase exponentially with the numberof bits. To avoid this in a high resolution design, a split-capacitor array is typically employed as shown in Fig. 1. Acommon problem associated with split-cap is that the parasiticcapacitance at the output of the sub-DAC and the fractionalvalue of the bridge capacitor both add uncertainty in thegain of the sub-DAC, and hence is a major limiting factor inaccuracy. Another problem in a split-cap array is that when theinputs are rail-to-rail, the output of the sub-DAC (VL nodes)can go beyond the rails [2]. To resolve the matching problem,Agnes et al. in [3] replaces the fractional bridge capacitor by aunit capacitor, but the design suffers from a constant gain error.Chen et al. in [4] pick a value of the bridge capacitor that isslightly larger than the desired size. A tunable capacitor is thenadded on the LSB side of the array to adjust the total weightof the sub-DAC in order to calibrate out the mismatches. Toresolve the over-range problem, Yoshioka et al. in [2] reducethe input range at the cost of SNR.In our prototype, an additional grounding capacitor CXis added to the VL nodes as shown in Fig. 1. By properlychoosing the value of CX , the value of the bridge capacitorConventional with Redundancy (4‐bit 5‐step)+‐1VIN+228VIN+VIN+VIN+228VCMVCM2 1VIN+ VIN+2 1 1VIN‐VIN‐VIN‐VIN‐ VIN‐ VIN‐+‐1228VREF2282 12 1 1VREFVREFVREF VREFVREF +‐1228VREF2282 12 1 1VREFVREFVREF VREFVREF+‐1228VREF2282 12 1 1VREFVREFVREFVREFVREFࢂࡵࡺା െ ࢂࡵࡺି ≶ ൅ ૛ ૡ⁄ ⋅ ࢂࡾࡱࡲࢂࡵࡺା െ ࢂࡵࡺି ≶ ૙ࢂࡵࡺା െ ࢂࡵࡺି ≶ െ ૟ ૡ⁄ ⋅ ࢂࡾࡱࡲFig. 2. Redundancy implementation using a conventional switching scheme.It has unequal error-tolerance windows during the “up” and “down” transition.can be an integer value. As an example, if the LSB DAC has 4-bit resolution (L = 4), when CX is chosen to be 14, the bridgecapacitor CBX has an integer value of 2. Moreover, since thesize of the CX capacitor is approximately equal to the sumof the remaining capacitors on the sub-DAC, the swing onVL nodes is effectively reduced by half, thereby removing theover-range problem and allowing rail-to-rail input swing. TheSNR is not affected because only the sub-DAC output swingis reduced in half. The uncertainty in the weights of sub-DACcapacitors is resolved by digital calibration.B. Redundancy ImplementationRedundancy helps improve conversion rate by allowingroom for errors, especially for large voltage jumps duringtransitions of the first few MSBs. A previous approach in-troduces redundancy into the SAR algorithm at the cost ofextra complexity and power [5]. The design requires onedecoder unit for each of the 2N capacitors, row and columnthermometer decoders, and an arithmetical unit to calculatethe next decision level. Another technique bypasses suchcomplexity and implements the redundancy algorithm directlyby sizing the capacitors with a sub-binary ratio [6]. Thetechnique in [6] allows the design to incorporate redundancydirectly without the previous complexity, but the search stepsbecome asymmetric, thus the tolerance to errors also becomesasymmetric. For example, to implement sub-binary searchsteps equal to [8, 2, 2, 2, 1], the capacitors in the DAC aresized proportional to the desired stepping sizes, as shown inFig. 2. After the first comparison, which is the sign bit, theinput is compared with either +(2/8)VREF or −(6/8)VREF ,stepping up/down by different amounts. In our prototype, weincorporate redundancy into tri-level based switching as shownby an example in Fig. 3. With this new approach, the steppingsize during the sub-binary search is directly proportional tothe sizing of the capacitors. After the first comparison, theinput is compared with (±2/8)VREF , stepping up/down bythe amount equal to the size of the first capacitor in the DAC.Fig. 4 shows the decision levels along with their highlightederror-tolerance windows (t). Using the conventional switchingscheme [6], the stepping sizes and the error-tolerance windowsare asymmetric, while in our work, they are symmetric aroundTri‐Level with Redundancyࢂࡵࡺା െ ࢂࡵࡺି ≶ ൅ ૛ ૡ⁄ ⋅ ࢂࡾࡱࡲࢂࡵࡺା െ ࢂࡵࡺି ≶ ૙+‐1VIN+22VIN+VIN+22VCMVCM2 1VIN+ VIN+2 1 1VIN‐VIN‐VIN‐ VIN‐ VIN‐+‐1VCM22VCMVCM222 1VCMVCM2 1 1VCMVCMVCM VCMVCM+‐1VCM22VCMVREF222 1VCMVCM2 1 1VCM VCM VCMVCM+‐1VCM22VCM222 1VCMVCM2 1 1VCMVCMVREF VCMVCMࢂࡵࡺା െ ࢂࡵࡺି ≶ െ ૛ ૡ⁄ ⋅ ࢂࡾࡱࡲ(4‐bit 5‐step)Fig. 3. Redundancy implementation with a tri-level switching algorithm. Ithas symmetric error-tolerance windows and 93% better energy efficiency.ࣕ ࢚ൌ૜ࣕ ࢚ൌ૜S ymme tr i cRedundancy (4‐bit 5‐step)(Differential Implementation)Conventional Switching IMCS Switchingcaps = [8 2 2 2 1 1] caps = [2 2 2 1 1]Highlighted error‐tolerance (࢚ࣕ) windows Actual decision levels: ܨ௢௨௧ ’sEXࣕ ࢚ൌ૜ࣕ ࢚ൌ૙A sy mme tr i cFig. 4. Comparison between implementing redundancy using the conven-tional versus tri-level switching algorithms.each decision level. The asymmetry implies that errors made inone direction can be corrected while it cannot be corrected inthe other direction. In real implementation, the input has equallikelihood of making errors in either direction. If the errortolerance windows are asymmetric, then redundancy algorithmwould not be as effective in correcting dynamic switchingerrors as it was originally designed for. Combining the tri-level switching algorithm with redundancy not only avoidsthe complexity in [5] to achieve symmetric search, but thealgorithm also achieves 93% better energy efficiency comparedto using a conventional switching algorithm.C. Digital Background CalibrationA new code-density based calibration algorithm is devel-oped for the redundant search algorithm. It can run in thebackground at the start of the ADC operation. Unlike theapproach in [6], this new digital calibration scheme does notrequire injection of a calibration signal, a redundant channel ora reference converter to calibrate against. In an N -bit M -stepredundant SAR ADC (in which M > N ), the actual decisionlevels (Fout’s) are a function of actual capacitor values and012345678910111213141500.20.40.60.8 1Raw digital output codeCode density (LSB)00000001001001011010110111101111[0.0][1.0][2.0][3.0][4.0][5.0][6.0][7.0]8 െ ܥଷ െ ܥଶ െ ܥଵ െ ܥ଴ ൈ 1 ൌ 0ݎଷݎଶݎଵݎ଴ܨ௢௨௧ ൌ 2ேିଵ ൅ ෍ 2 ∙ ݎ௜ െ 1 ൈ ܥ௜ ൅ ݎ଴ െ 1 ൈ ܥ଴ெିଵ௜ୀଵ8 െ ܥଷ െ ܥଶ െ ܥଵ ൅ ܥ଴ ൈ 0 ൌ 18 െ ܥଷ െ ܥଶ ൅ ܥଵ െ ܥ଴ ൈ 1 ൌ 28 ൅ ܥଷ ൅ ܥଶ െ ܥଵ ൅ ܥ଴ ൈ 0 ൌ 58 ൅ ܥଷ ൅ ܥଶ ൅ ܥଵ െ ܥ଴ ൈ 1 ൌ 68 ൅ ܥଷ ൅ ܥଶ ൅ ܥଵ ൅ ܥ଴ ൈ 0 ൌ 78 ൅ ܥଷ െ ܥଶ ൅ ܥଵ െ ܥ଴ ൈ 1 ൌ 48 െ ܥଷ ൅ ܥଶ െ ܥଵ ൅ ܥ଴ ൈ 0 ൌ 3ܥଷ, ܥଶ, ܥଵ, ܥ଴ ൌ 1,1,1,1SolutionCode Density (LSB)CumulativeHistogramFig. 5. Demonstration of the new digital background calibration algorithm.raw output bits (ri’s) as given in Equation 1.Fout = 2N−1 +M−1∑i=1Ci × (2× ri − 1) + C0 × (r0 − 1) (1)The calibration algorithm finds the true weights (Ci’s) thatmap the raw output bits into an N -bit digitalized outputaccurately. A histogram is created by counting the numberof occurrences of the 2M raw output codes. Because ofredundancy, many codes never show up at the outputs. If theinput signal is uniformly distributed over the full scale andif the ADC is noise free, with enough samples, the numberof occurrences of each code is proportional to its bin width;therefore, the ratio of the counts to the total number of samplescan estimate the ratio of bin width to the full input scale. Fig. 5shows a simple example that demonstrates the calibrationprocedure. Many code bins (bins 3, 4, etc.) are empty due toredundancy. The counts are accumulated to form a cumulativehistogram, from which estimates of the actual decision levels(Fout’s) for each code bin are obtained. With Fout’s and theraw output bits, an equation associated with each code binis formulated. By subtracting the neighboring equations andputting the results into a matrix form, we obtain a sparsematrix filled with mostly 0’s and some entries with ±1 and±2. Even though the size of the matrix can grow exponentiallywith the number of bits, since it is a sparse matrix with onlya few distinct elements, techniques such as the Markowitzreordering can be used to minimize the fill-in and solve thematrix efficiently. As shown in Fig. 5, we are able to obtainthe actual capacitor sizes by solving these equations.For input signals with non-uniform probability density, thehistogram is locally normalized over a small input range forwhich the probability density of input remains reasonablyconstant, which makes the calibration independent of the inputsignal waveform. It can be shown that, with enough samples,random noise does not affect the capacitor value extraction.The calibration is tested with a sine wave, ramp, and uniformly+‐…VREF+VREF‐VCMVinREADY GENERATORPULSEGENERATORDIGITALLOGICBootstrapped SwitchesOUTPUT REGISTERSSub‐DAC Main‐DACr0r14r15࡯࢙࢛࢈ࡰ࡭࡯,ࢋࢌࢌ ൌ∑ ࡯࢏૟࢏ୀ૙ ൈ ࡯࡮∑ ࡯࢏૟࢏ୀ૙ ൅ ࡯࡮ ൅ ࡯ࢄൌ૚ૡ૚ૠ. ૞VM+……C7 C8 C15…C0 C1 C6CX…CBCBC7 C8 C15C0 C1 C6CXVL+ VM‐VL‐Effecitve sub‐DAC weight inreference to the main‐DAC :࡯࢙࢛࢈ࡰ࡭࡯,ࢋࢌࢌCalibrationEngineb11b10b0…50241610643212843110.50.515CBC6C5C4C3C2C1C0CXC15C14C13C12C11C10C9C8C7Fig. 6. The overall architecture of the protytype ADC.random inputs without prior knowledge of the input and isshown to be insensitive to the input waveform.III. MEASUREMENT RESULTFig. 6 shows the overall architecture of the ADC. Anasynchronous implementation, similar to [7], is used to speedup the sampling rates and to avoid large jitter by not bringinga high speed clock from off chip. Digital logic circuits, suchas the ready generator, pulse generator and digital controls, aredesigned using dynamic logic to improve energy efficiency andspeed. No static pre-amplifier is placed in front of the latchcomparator to further increase the sampling rate. Bootstrappedswitches are used for all reference voltages to improve linearityand all capacitors are sized to be integer related.Two identical channels are time-interleaved. Sixteen rawoutput bits are generated for 12-bit effective resolution. Thecalibration is done off chip. The estimated calibration poweris added to the total power consumption. The prototype ADCis fabricated in standard 1P9M 65nm LP CMOS with 1.2Vsupply. The active die area is 0.083mm2 (330µm×125µm×2).The die micrograph is shown in Fig. 7. The implementationallows full input swing (2.4Vp−p) because of the CX capacitor.The DAC is implemented with standard MOM cap with a totalcapacitance of 1.6pF. Several chips are measured and all themeasurement is done at room temperature.While the ADC operates at 50MS/s, a 24.7MHz full-scale sine wave input is used to test the static and dynamicperformance. Fig. 8 shows the measured DNL and INL beforeand after the calibration. Before calibration, the maximumDNL and INL errors are +1.3/ − 1.1LSB12 and +14.3/ −14.0LSB12, respectively. The linearity is mainly limited by thecapacitor mismatch. Normal sine wave input is used here as thecalibration stimuli and 1 million data points are collected. Af-ter calibration, the maximum DNL and INL errors are reducedto +0.5/ − 0.7LSB12 and +1.0/ − 0.9LSB12, respectively.Fig. 9 shows the measured dynamic performance, based on8192-point FFT. Before calibration, the ADC achieves 52.4dBof SNDR, 51.9dB of SFDR and 8.2b ENOB; after calibration,the ADC achieves 67.4dB of SNDR, 78.1dB of SFDR and10.9b ENOB. The SNDR/SFDR versus input frequency at50MS/s and the performance summary are provided in Fig. 10.330µm1 25 µm330µm125µmFig. 7. Micrograph of the ADC chip in standard 65nm LP CMOS technology.0 1000 2000 3000 4000-1-0.500.51DIGITAL OUTPUT CODE0 1000 2000 3000 4000-1.5-1-0.500.511.5DIGITAL OUTPUT CODE0 1000 2000 3000 4000-1-0.500.511.5DIGITAL OUTPUT CODE0 1000 2000 3000 4000-20-15-10-505101520DIGITAL OUTPUT CODEINL = +1.0/-0.9DNL = +0.5/-0.7INL = +14.3/-14.0DNL = +1.3/-1.1Before CalibrationAfter CalibrationFig. 8. Measured DNL/INL plot with 1.2V supply at 50MS/s with a 24.7MHzinput signal.Total power consumption including the estimated calibrationand reference power is 2.1mW for 21.9fJ/conv.-step FoM.Fig. 11 shows the comparison with the state-of-the-art.ACKNOWLEDGMENTThe authors would like to thank Anantha Chandrakasan forvaluable discussions, the MIT/Masdar Institute CooperativeProgram for funding and TSMC for chip fabrication.REFERENCES[1] Y. Chen, S. Tsukamoto, and T. Kuroda, “A 9b 100MS/s 1.46mW SARADC in 65nm CMOS,” in A-SSCC, 2009, pp. 145–148.[2] M. Yoshioka et al., “A 10b 50MS/s 820µW SAR ADC with On-ChipDigital Calibration,” in ISSCC, 2010, pp. 384–385.[3] A. Agnes et al., “A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with Time-Domain Comparator,” in ISSCC, 2008, pp. 246–247.[4] Y. Chen et al., “Split Capacitor DAC Mismatch Calibration in SuccessiveApproximation ADC,” in CICC, Sept. 2009, pp. 279–282.[5] F. Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approxi-mation ADC in 0.13µm CMOS,” in ISSCC, 2002, pp. 176–177.[6] W. Liu et al., “A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADCAchieving over 90dB SFDR,” in ISSCC, 2010, pp. 380–381.[7] S.-W. Chen and R. Brodersen, “A 6-bit 600-MS/s 5.3-mW AsynchronousADC in 0.13-mum CMOS,” JSSC, vol. 41, no. 12, pp. 2669–2680, 2006.0 5 10 15 20 25-120-100-80-60-40-200d B  After CalibrationSNDR = 67.4 dB, SFDR = 78.1 dB, ENOB = 10.9bInput Frequency (MHz)0 5 10 15 20 25-120-100-80-60-40-200d B  Before CalibrationSNDR = 51.4 dB, SFDR = 51.9 dB, ENOB = 8.2bInput Frequency (MHz)Fig. 9. Measured spectrum data with 1.2V supply at 50MS/s with a 24.7MHzinput signal.0 5 10 15 20 25 30404550556065707580fin (MHz)S NDR/ SF DR ( dB)  SNDR before cal.SNDR after cal.SFDR before cal.SFDR after cal.܎܋ܔܓ ൌ ૞૙ۻ܁/ܛ Technology 65nm CMOS LP ProcessActive Area 0.083 mm2 (125µm x 330µm x 2)Supply Voltage 1.2 VSignal Swing 2.4 Vpp, differentialSample Rate 50 MS/s 10 MS/sSNDR 67.4 dB 67.65 dBENOB 10.9 bit 11.0 bitAnalog Power 912 µW(DAC switching power: 283 µW)185 µW(DAC switching power: 45 µW)Digital Power 1.163mW 215 µWTotal Power 2.09 mW 400 µWFoM@ Nyquist 21.9 fJ/step 19.5 fJ/stepFig. 10. Measured dynamic performance at different input frequencies andsummary of the measurement results.20 30 40 50 60 70 80100101102103104SNDR [dB]E ne rg y- Pe r- Co nv er si on  [ pJ ]  ISSCC 09-12VLSI 09-12Our WorkFoM=10fJ/stepFoM=100fJ/step50MS/sFig. 11. Comparison with the state-of-the-art ADCs (data from B.Murmann, “ADC Performance Survey 1997-2012,” http://www.stanford.edu/∼murmann/adcsurvey.html).

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A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

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