전근대 토지대장과 지적도의 대화형 분석을 위한 시각화 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 서진욱.We propose an interactive visualization design tool, called JigsawMap, for analyzing and mapping historical textual cadasters. A cadaster is an official register that records land properties (e.g., location, ownership, value and size) for land valuation and taxation. Such mapping of old and new cadasters can help historians understand the social and economic background of changes in land uses or ownership. JigsawMap can effectively connect the past land survey results to modern cadastral maps. In order to accomplish the connection process, three steps are performed: (1) segmentation of cadastral map, (2) visualization of textual cadastre, (3) and mapping interaction. We conducted usability studies and long term case studies to evaluate JigsawMap, and received positive responses. We summarize the evaluation results and present design guidelines for participatory design projects with historians. Followed by our study on JigsawMap, we further investigated on each components of our tool for more scalable map connection. First, we designed a hybrid algorithm to semi-automatically segment land pieces on cadastral map. The original JigsawMap provides interface for user to segment land pieces and the experiment result shows that segmentation algorithm accurately extracts the regions. Next, we reconsidered the visual encoding and simplified it to make textual cadastre more scalable. Since the former visual encoding relies on traditional map legend, the visual encoding can be selected based on user expert level. Finally, we redesigned layout algorithm to generate a better initial layout. We used evolution algorithm to articulate ambiguity problem of textual cadastre and the result less suffered from overlapping problem. Overall, our visualization design tool will provide an accurate segmentation result, give the user an option to select visual encoding that suits on their expert level, and generate more readable initial layout which gives an overview of cadastre layout.Chapter 1 Introduction 1 1.1 Background & Motivation 1 1.2 Main Contribution 7 1.3 Organization of the Dissertation 8 Chapter 2 Related Work 11 2.1 Map Data Visualization 11 2.2 Graph Layout Algorithms 13 2.3 Collaborative Map Editing Service 14 2.4 Map Image Segmentation 15 2.5 Premodern Cadastral Maps 17 2.6 Assessing Measures for Cartogram 18 Chapter 3 Visualizing and Mapping Premodern Textual Cadasters to Cadastral Maps 20 3.1 Textual Cadastre 21 3.2 Cadastral Maps 24 3.3 Paper-based Mapping Process and Obstacles 24 3.4 Task Flow in JigsawMap 26 3.5 Design Rationale 32 3.6 Evaluation 34 3.7 Discussion 40 3.8 Design Guidelines When Working with Historians 42 Chapter 4 Accurate Segmentation of Land Regions in Historical Cadastral Maps 44 4.1 Segmentation Pipeline 45 4.2 Preprocessing 46 4.3 Removal of Grid Line 48 4.4 Removal of Characters 52 4.5 Reconstruction of Land Boundaries 53 4.6 Generation of Polygons 55 4.7 Experimental Result 56 4.8 Discussion 59 Chapter 5 Approximating Rectangular Cartogram from Premodern Textual Cadastre 62 5.1 Challenges of the Textual Cadastre Layout 62 5.2 Quality Measures for Assessing Rectangular Cartogram 64 5.3 Quality Measures for Assessing Textual Cadastre 65 5.4 Graph Layout Algorithm 66 5.5 Results 72 5.6 Discussion 73 Chapter 6 Design of Scalable Node Representation for a Large Textual Cadastre 78 6.1 Motivation 78 6.2 Visual Encoding in JigsawMa 80 6.3 Challenges of Current Visual Encoding 81 6.4 Compact Visual Encoding 83 6.5 Results 84 6.6 Discussion 86 Chapter 7 Conclusion 88 Bibliography 90 Abstract in Korean 101Docto

축차 비교형 아날로그-디지털 변환기의 성능 향상을 위한 기법에 대한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 김수환.This thesis is written about a performance enhancement technique for the successive-approximation-register analog-to-digital converter (SAR ADC). More specifically, it focuses on improving the resolution of the SAR ADC. The basic operation principles and the architecture of the conventional SAR ADC is examined. To gain insight on areas of improvement, a deeper look is taken at the building components of the SAR ADC. Design considerations of these components are discussed, along with the performance limiting factors in the resolution and bandwidth domains. Prior works which challenge these problems in order to improve the performance of the SAR ADC are presented. To design SAR ADCs, a high-level modeling is presented. This model includes various non-ideal effects that occur in the design and operation. Simulation examples are shown how the model is efficient and useful in the initial top-level designing of the SAR ADC. Then, the thesis proposes a technique that can enhance the resolution. The SAR ADC using integer-based capacitor digital-to-analog converter (CDAC) exploiting redundancy is presented. This technique improves the mismatch problem that arises with the widely used split-capacitor structure in the CDAC of the SAR ADC. Unlike prior works, there is no additional overhead of additional calibration circuits or reference voltages. A prototype SAR ADC which uses the integer-based CDAC exploiting redundancy is designed for automotive applications. Measurement results show a resolution level of 12 bits even without any form of calibration. Finally, the conclusion about the operation and effectiveness on the proposed technique is drawn.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 7 2.1 INTRODUCTION 7 2.2 OPERATION PRINCIPLE OF THE CONVENTIONAL SAR ADC 8 2.2.1. OVERVIEW OF THE OPERATION 8 2.2.2. SAMPLING PHASE 10 2.2.3. CONVERSION PHASE 11 2.3 STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.1. FULL STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.2. CAPACITOR DIGITAL-TO-ANALOG CONVERTER (CDAC) 17 2.3.3. COMPARATOR 21 2.3.4. CONTROL LOGIC 23 2.4 PERFORMANCE LIMITING FACTORS 24 2.4.1. RESOLUTION LIMITING FACTORS 24 2.4.2. OPERATION BANDWIDTH LIMITING FACTORS 28 2.5 PRIOR WORK 30 2.5.1. INTRODUCTION 30 2.5.2. SPLIT-CAPACITOR STRUCTURE OF THE CDAC 31 2.5.3. REDUNDANCY AND CDAC WEIGHT DISTRIBUTION 33 2.5.4. ASYNCHRONOUS CONTROL LOGIC 36 2.5.5. CALIBRATION TECHNIQUES 37 2.5.4. DOUBLE-SAMPLING TECHNIQUE FOR SAMPLING TIME REDUCTION 38 2.5.6. TWO-COMPARATOR ARCHITECTURE FOR COMPARATOR DECISION TIME REDUCTION 40 2.5.7. MAJORITY VOTING FOR RESOLUTION ENHANCEMENT 41 CHAPTER 3 MODELING OF THE SAR ADC 43 3.1 INTRODUCTION 43 3.2 WEIGHT DISTRIBUTION OF THE CAPACITOR DAC AND REDUNDANCY 44 3.3 SPLIT-CAPACITOR ARRAY TECHNIQUE 47 3.4 PARASITIC EFFECTS OF THE CAPACITOR DAC 48 3.5 MISMATCH MODEL OF THE CAPACITOR DAC 51 3.6 SETTLING ERROR OF THE DAC 53 3.7 COMPARATOR DECISION ERROR 58 3.8 DIGITAL ERROR CORRECTION 59 CHAPTER 4 SAR ADC WITH INTEGER-BASED SPLIT-CDAC EXPLOITING REDUNDANCY FOR AUTOMOTIVE APPLICATIONS 60 4.1 INTRODUCTION 60 4.2 MOTIVATION 61 4.3 PRIOR WORK ON RESOLVING THE SPLIT-CAPACITOR CDAC MISMATCH FOR THE SAR ADC 64 4.3.1. CONVENTIONAL SPLIT-CAPACITOR CDAC FOR THE SAR ADC 64 4.3.2. SPLITTING THE LAST STAGE OF THE LSB-SIDE OF THE CDAC 66 4.3.3. CALIBRATION OF THE NON-INTEGER MULTIPLE BRIDGE CAPACITOR 67 4.3.4. INTEGER-MULTIPLE BRIDGE CAPACITOR WITH LSB-SIDE CAPACITOR ARRAY CALIBRATION 68 4.3.5. OVERSIZED BRIDGE CAPACITOR WITH ADDITIONAL FRACTIONAL REFERENCE VOLTAGE 69 4.4 PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR THE SAR ADC 70 4.5 CIRCUIT DESIGN 72 4.5.1. PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR SAR ADC 72 4.5.2. COMPARATOR 74 4.5.3. CONTROL LOGIC 75 4.6 IMPLEMENTATION AND EXPERIMENTAL RESULTS 76 4.6.1. LAYOUT 76 4.6.2. MEASUREMENT RESULTS AND CONCLUSIONS 82 CHAPTER 5 CONCLUSION AND FUTURE WORK 86 5.1 CONCLUSION 86 5.2 FUTURE WORK 87 APPENDIX. SAR ADC USING THRESHOLD-CONFIGURING COMPARATOR FOR ULTRASOUND IMAGING SYSTEMS 89 BIBLIOGRAPHY 120Docto

용인동백 생태도시 기본계획

학위논문(석사)--서울대학교 환경대학원 :환경조경학과,1998.Maste

A High Resolution Time-to-Digital Converter Using Open-loop Delay-Locked Loop

학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2010.2.Maste