A study of high-speed AD and DA converters using redundancy techniques Interim report, May 10, 1963 - May 9, 1964

High speed analog-to-digital converters compared using redundancy encoding technique

Some variations of tunnel diode pulse generator circuits

Variations of tunnel diode pulse generator circuit

The design of an array processor for pattern recognition studies

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering, 1960.MIT copy bound with: The electrostatic synchronous motor for smear camera application / Saul Fox Stanten. 1960. -- Design and construction of a thermoelectric dew point measuring device / Tom Neil Thiele. 1960. -- A study of modification in the German noun phrase / Robert Symons Troth. 1960. -- A selective signalling device for paging or call systems / George M. Walsh. 1960. -- A dual channel transistor transmitter for sensory aid research / Stephen B. Weinstein. 1960. -- A low cost, solid state digital converter / John Edward Yates. 1960.Includes bibliographical references (leaf 45).by Herbert Martin Shanzer.B.S

Spiers Memorial Lecture: Molecular mechanics and molecular electronics

We describe our research into building integrated molecular electronics circuitry for a diverse set of functions, and with a focus on the fundamental scientific issues that surround this project. In particular, we discuss experiments aimed at understanding the function of bistable [2]rotaxane molecular electronic switches by correlating the switching kinetics and ground state thermodynamic properties of those switches in various environments, ranging from the solution phase to a Langmuir monolayer of the switching molecules sandwiched between two electrodes. We discuss various devices, low bit-density memory circuits, and ultra-high density memory circuits that utilize the electrochemical switching characteristics of these molecules in conjunction with novel patterning methods. We also discuss interconnect schemes that are capable of bridging the micrometre to submicrometre length scales of conventional patterning approaches to the near-molecular length scales of the ultra-dense memory circuits. Finally, we discuss some of the challenges associated with fabricated ultra-dense molecular electronic integrated circuits

Nanoelectronics

In this chapter we intend to discuss the major trends in the evolution of microelectronics and its eventual transition to nanoelectronics. As it is well known, there is a continuous exponential tendency of microelectronics towards miniaturization summarized in G. Moore's empirical law. There is consensus that the corresponding decrease in size must end in 10 to 15 years due to physical as well as economical limits. It is thus necessary to prepare new solutions if one wants to pursue this trend further. One approach is to start from the ultimate limit, i.e. the atomic level, and design new materials and components which will replace the present day MOS (metal-oxide-semi- conductor) based technology. This is exactly the essence of nanotechnology, i.e. the ability to work at the molecular level, atom by atom or molecule by molecule, to create larger structures with fundamentally new molecular orga- nization. This should lead to novel materials with improved physical, chemi- cal and biological properties. These properties can be exploited in new devices. Such a goal would have been thought out of reach 15 years ago but the advent of new tools and new fabrication methods have boosted the field. We want to give here an overview of two different subfields of nano- electronics. The first part is centered on inorganic materials and describes two aspects: i) the physical and economical limits of the tendency to miniaturiza- tion; ii) some attempts which have already been made to realize devices with nanometric size. The second part deals with molecular electronics, where the basic quantities are now molecules, which might offer new and quite interest- ing possibilities for the future of nanoelectronicsComment: HAL : hal-00710039, version 2. This version corrects some aspect concerning the metal-insulator-metal without dot

Complementary tunnel gate topology to reduce crosstalk effects

Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated