Sliding Trellis-Based Frame Synchronization

Frame Synchronization (FS) is required in several communication standards in order to recover the individual frames that have been aggregated in a burst. This paper proposes a low-delay and reducedcomplexity Sliding Trellis (ST)-based FS technique, compared to our previously proposed trellis-based FS method. Each burst is divided into overlapping windows in which FS is performed. Useful information is propagated from one window to the next. The proposed method makes use of soft information provided by the channel, but also of all sources of redundancy present in the protocol stack. An illustration of our STbased approach for the WiMAX Media Access Control (MAC) layer is provided. When FS is performed on bursts transmitted over Rayleigh fading channel, the ST-based approach reduces the FS latency and complexity at the cost of a very small performance degradation compared to our full complexity trellis-based FS and outperforms state-of-the-art FS techniques.Comment: IEEE International Conference on Communication (2011

Joint Protocol-Channel Decoding for Robust Frame Synchronization

International audienceIn many communication standards, several variable length frames generated by some source coder may be aggregated at a given layer of the protocol stack in the same burst to be transmitted. This decreases the signalization overhead and increases the throughput. However, after a transmission over a noisy channel, Frame Synchronization (FS), i.e., recovery of the aggregated frames, may become difficult due to errors affecting the bursts. This paper proposes several robust FS methods making use of the redundancy present in the protocol stack combined with channel soft information. A trellis-based FS algorithm is proposed first. Its efficiency is obtained at the cost of a large delay, since the whole burst must be available before beginning the processing, which might not be possible in some applications. Thus, a low-delay and reduced-complexity Sliding Window-based variant is introduced. Second, an improved version of an on-the-fly three-state automaton for FS is proposed. Bayesian hypothesis testing is performed to retrieve the correct FS. These methods are compared in the context of the WiMAX MAC layer when bursts are transmitted over Rayleigh fading channels

Synchronization for capacity -approaching coded communication systems

The dissertation concentrates on synchronization of capacity approaching error-correction codes that are deployed in noisy channels with very low signal-to-noise ratio (SNR). The major topics are symbol timing synchronization and frame synchronization.;Capacity-approaching error-correction codes, like turbo codes and low-density parity-check (LDPC) codes, are capable of reaching very low bit error rates and frame error rates in noisy channels by iterative decoding. To fully achieve the potential decoding capability of Turbo codes and LDPC codes, proper symbol timing synchronization, frame synchronization and channel state estimation are required. The dissertation proposes a joint estimator of symbol time delay and channel SNR for symbol timing recovery, and a maximum a posteriori (MAP) frame synchronizer for frame synchronization.;Symbol timing recovery is implemented by sampling and interpolation. The received signal is sampled multiple times per symbol period with unknown delay and unknown SNR. A joint estimator estimates the time delay and the SNR. The signal is rebuilt by interpolating available samples using estimated time delay. The intermediate decoding results enable decision-feedback estimation. The estimates of time delay and SNR are refined by iterative processing. This refinement improves the system performance significantly.;Usually the sampling rate is assumed to be a strict integer multiple of the symbol rate. However, in a practical system the local oscillators in the transmitter and the receiver may have random drifts. Therefore the sampling rate is no longer an exact multiple of the symbol rate, and the sampling time follows a random walk. This random walk may harm the system performance severely. The dissertation analyzes the effect of random time walks and proposes to mitigate the effect by overlapped sliding windows and iterative processing.;Frame synchronization is required to find the correct boundaries of codewords. MAP frame synchronization in the sense of minimizing the frame sync failure rate is investigated. The MAP frame synchronizer explores low-density parity-check attributes of the capacity-approaching codes. The accuracy of frame synchronization is adequate for considered coded systems to work reliably under very low SNR

Insertion/deletion error correction using path pruned convolutional codes and extended prefix codes

Synchronization error correction has been under discussion since the early development of coding theory. In this research report a novel coding system based on the previous done work on path-pruned convolutional codes and extended prefix synchronization codes is presented. This new coding scheme is capable of correcting insertion, deletion and synchronization errors. A codebook has been constructed that contains synchronization patterns made up of a constraint part (maker sequence) and an unconstraint part based on the concept of extended prefix codes. One of these synchronization error patterns are padded in front of each frame. This process is done by mapping information bit to a corresponding bit sequence using a mapping table. The mapping table is constructed by using path-pruning process. An original rate convolutional code is first punctured using a desired puncturing matrix to make enough paths available at each state of the trellis. The desired paths are then pruned and matches to the extended prefix codebook constructed. The path pruning process consists of a feedback mapper attached in front of the original rate parent convolutional encoder with puncturing. The state of the convolutional encoder is fed back to the mapper which maps first information bit of the frame into a multi-bit sequence that is fed into the convolutional encoder with puncturing and thus produces one of the synchronization patterns contained within the codebook constructed. The remaining bits of the frame are encoded normally using convolutional encoding with a puncturing process only. This process is repeated periodically depending on the condition of the channel. Simulations were performed to evaluate the ability of new system to resynchronize and correct insertion/deletion and synchronization errors at the receiver, from which favorable results were obtained. Simulations were performed with different synchronization pattern (extended prefix code word) lengths, different constraint lengths of the parent encoder and using Reed-Solomon codes as outer code in concatenation with new coding system. A complete concatenated coding system is thus demonstrated and studied that resynchronizes and corrects insertion, deletion and substitution errors

Synchronization Techniques for Burst-Mode Continuous Phase Modulation

Synchronization is a critical operation in digital communication systems, which establishes and maintains an operational link between transmitter and the receiver. As the advancement of digital modulation and coding schemes continues, the synchronization task becomes more and more challenging since the new standards require high-throughput functionality at low signal-to-noise ratios (SNRs). In this work, we address feedforward synchronization of continuous phase modulations (CPMs) using data-aided (DA) methods, which are best suited for burst-mode communications. In our transmission model, a known training sequence is appended to the beginning of each burst, which is then affected by additive white Gaussian noise (AWGN), and unknown frequency, phase, and timing offsets. Based on our transmission model, we derive the Cramer-Rao bound (CRB) for DA joint estimation of synchronization parameters. Using the CRB expressions, the optimum training sequence for CPM signals is proposed. It is shown that the proposed sequence minimizes the CRB for all three synchronization parameters asymptotically, and can be applied to the entire CPM family. We take advantage of the simple structure of the optimized training sequence in order to design a practical synchronization algorithm based on the maximum likelihood (ML) principles. The proposed DA algorithm jointly estimates frequency offset, carrier phase and symbol timing in a feedforward manner. The frequency offset estimate is first found by means of maximizing a one dimensional function. It is then followed by symbol timing and carrier phase estimation, which are carried out using simple closed-form expressions. We show that the proposed algorithm attains the theoretical CRBs for all synchronization parameters for moderate training sequence lengths and all SNR regions. Moreover, a frame synchronization algorithm is developed, which detects the training sequence boundaries in burst-mode CPM signals. The proposed training sequence and synchronization algorithm are extended to shaped-offset quadrature phase-shift keying (SOQPSK) modulation, which is considered for next generation aeronautical telemetry systems. Here, it is shown that the optimized training sequence outperforms the one that is defined in the draft telemetry standard as long as estimation error variances are considered. The overall bit error rate (BER) plots suggest that the optimized preamble with a shorter length can be utilized such that the performance loss is less than 0.5 dB of an ideal synchronization scenario

Unified turbo/LDPC code decoder architecture for deep-space communications

Deep-space communications are characterized by extremely critical conditions; current standards foresee the usage of both turbo and low-density-parity-check (LDPC) codes to ensure recovery from received errors, but each of them displays consistent drawbacks. Code concatenation is widely used in all kinds of communication to boost the error correction capabilities of single codes; serial concatenation of turbo and LDPC codes has been recently proven effective enough for deep space communications, being able to overcome the shortcomings of both code types. This work extends the performance analysis of this scheme and proposes a novel hardware decoder architecture for concatenated turbo and LDPC codes based on the same decoding algorithm. This choice leads to a high degree of datapath and memory sharing; postlayout implementation results obtained with complementary metal-oxide semiconductor (CMOS) 90 nm technology show small area occupation (0.98 mm 2 ) and very low power consumption (2.1 mW)