'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
Deep-space communications are characterized by extremely
critical conditions; current standards foresee the usage of both turbo
and low-density-parity-check (LDPC) codes to ensure recovery from
received errors, but each of them displays consistent drawbacks.
Code concatenation is widely used in all kinds of communication to
boost the error correction capabilities of single codes; serial
concatenation of turbo and LDPC codes has been recently proven
effective enough for deep space communications, being able to
overcome the shortcomings of both code types. This work extends
the performance analysis of this scheme and proposes a novel
hardware decoder architecture for concatenated turbo and LDPC
codes based on the same decoding algorithm. This choice leads to a
high degree of datapath and memory sharing; postlayout
implementation results obtained with complementary metal-oxide
semiconductor (CMOS) 90 nm technology show small area
occupation (0.98 mm
2
) and very low power consumption (2.1 mW)
