Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps

Improving the Convergence of Vector Fitting for Equivalent Circuit Extraction From Noisy Frequency Responses

The vector fitting (VF) algorithm has become a common tool in electromagnetic compatibility and signal integrity studies. This algorithm allows the derivation of a rational approximation to the transfer matrix of a given linear structure starting from measured or simulated frequency responses. This paper addresses the convergence properties of a VF when the frequency samples are affected by noise.We show that small amounts of noise can seriously impair or destroy convergence. This is due to the presence of spurious poles that appear during the iterations. To overcome this problem we suggest a simple modification of the basic VF algorithm, based on the identification and removal of the spurious poles. Also, an incremental pole addition and relocation process is proposed in order to provide automatic order estimation even in the presence of significant noise.We denote the resulting algorithm as vector fitting with adding and skimming (VF-AS). A thorough validation of the VF-AS algorithm is presented using a Monte Carlo analysis on synthetic noisy frequency responses. The results show excellent convergence and significant improvements with respect to the basic VF iteration scheme. Finally, we apply the new VF-AS algorithm to measured scattering responses of interconnect structures and networks typical of high-speed digital systems

Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS

Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description. At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance. For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

40 Gb/s data transmission over a 1-m-long multimode polymer spiral waveguide for board-level optical interconnects

Optical interconnects have attracted considerable attention for use in short-reach communication links within high performance electronic systems, such as data centres, supercomputers and data storage systems. Multimode polymer waveguides in particular, constitute an attractive technology for use in board-level interconnects as they can be cost-effectively integrated onto standard PCBs and allow system assembly with relaxed alignment tolerances. However, their highly-multimoded nature raises important concerns about their bandwidth limitations and their potential to support very high on-board data rates. In this paper, we report record error-free (BER<10-12) 40 Gb/s data transmission over a 1 m long multimode polymer spiral waveguide and present thorough studies on the waveguide bandwidth performance. The frequency response of the waveguide is investigated under a wide range of launch conditions and in the presence of input spatial offsets which are expected to be highly-likely in real-world systems. A robust bandwidth performance is observed with a bandwidth-length product of at least 35 GHz×m for all launch conditions studied. The reported results clearly demonstrate the potential of this technology for use in board-level interconnects, and indicate that data rates of at least 40 Gb/s are feasible over waveguide lengths of 1 m.This work was supported by the U.K. EPSRC through the Centre for Advanced Photonics and Electronics (CAPE), and the Swedish Foundation for Strategic Research.This is the final version of the article. It was first published by IEEE at http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=696085

Circuit design and analysis for on-FPGA communication systems

On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

Entire domain basis function expansion of the differential surface admittance for efficient broadband characterization of lossy interconnects

This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements