Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes

Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines (recess distance, bias voltage) to follow to make them work efficiently in such technology. To do so, both photodiode arrays and active pixel sensors are used. After 2.2 Mrad(SiO2), the studied sensors are fully functional and most of the radiation hardened photodiodes exhibit radiation induced dark current values more than one order of magnitude lower than the standard photodiode

Memcapacitive Devices in Logic and Crossbar Applications

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7x less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1,500x for the MNIST dataset and a factor of about 1,000x for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs

La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) es considera un possible successor de l'MOSFET. A causa del seu mecanisme alternatiu de transport de corrent, conegut com a túnel de banda a banda (B2B), el pendent subumbral en TFET pot fer-se inferior al límit de 60 mV / dec. Per comprendre i estimar el comportament dels TFET, no només com un element únic sinó també a nivell de circuit, es requereix un model compacte d'aquest dispositiu. En aquesta tesi es presenta un model basat en càrrega per descriure el comportament capacitiu d'un TFET de doble porta (DG TFET). No obstant això, la simplicitat i la flexibilitat de el model permeten usar-lo per a un altre tipus d'estructures TFET, com els TFET planars o de nanofils d'una sola porta (SG TFETs). El model és verificat amb les simulacions TCAD, així com amb mesures experimentals de TFET fabricats. El model de capacitància també inclou l'efecte dels elements paràsits. A més, en el context d'aquest treball també s'investiga la influència dels contactes de barrera Schottky en el comportament capacitiu dels TFET. Aquest model finalment es combina amb un model DC compacte existent per formar un model TFET compacte complet. A continuació, el model compacte s'implementa per a simulacions transitòries de circuits oscil·ladors d'anell basats en TFET.La miniaturización de los MOSFET en los circuitos integrados ha elevado la tecnología microelectrónica. Esta tendencia también aumenta el grado de complejidad de estos circuitos y sus componentes básicos. En los MOSFET convencionales, la corriente se basa en la emisión termoiónica de portadores de carga, que por ello limita la pendiente subumbral en estos transistores a 60 mV/dec. Por tanto, para superar este límite y continuar con la miniaturización para mantener el ritmo de la ley de Moore, se requieren estructuras alternativas. Entre estas, el transistor de efecto de campo por túnel (TFET) se considera un posible sucesor del MOSFET. Debido a su mecanismo alternativo de transporte de corriente, conocido como túnel de banda a banda (B2B), la pendiente subumbral en TFET puede hacerse inferior al límite de 60 mV/dec. Para comprender y estimar el comportamiento de los TFET, no sólo como un elemento único sino también a nivel de circuito, se requiere un modelo compacto de este dispositivo. En esta tesis se presenta un modelo basado en carga para describir el comportamiento capacitivo de un TFET de doble puerta (DG TFET). Sin embargo, la simplicidad y la flexibilidad del modelo permiten usarlo para otro tipo de estructuras TFET, como los TFET planares o de nanohílos de una sola puerta (SG TFETs). El modelo es verificado con las simulaciones TCAD, así como con medidas experimentales de TFET fabricados. El modelo de capacitancia también incluye el efecto de los elementos parásitos. Además, en el contexto de este trabajo también se investiga la influencia de los contactos de barrera Schottky en el comportamiento capacitivo de los TFET. Este modelo finalmente se combina con un modelo DC compacto existente para formar un modelo TFET compacto completo. A continuación, el modelo compacto se implementa para simulaciones transitorias de circuitos osciladores de anillo basados en TFET.Miniaturization of the MOSFETs on the integrated circuits has elevated the microelectronic technology. This trend also increases the degree of complexity of these circuits and their building blocks. In conventional MOSFETs the current is based on the thermionic—emission of charge carrier, which therefore limits the subthreshold swing in these transistors to 60 mV/dec. Hence, to overcome this limit and continue with down scaling to keep pace with the Moor’s law, alternative structures are required. Among these, the tunnel—field—effect transistor (TFET) is considered as a potential successor of the MOSFET. Due to its alternative current transport mechanism, known as band—to—band (B2B) tunneling, the subthreshold swing in TFETs can overcome the 60 mV/dec limit. In order to comprehend and estimate the behavior of TFETs, not only as a single element but also on the circuit level, a compact model of this device is required. In this dissertation a charge –based model to describes the capacitive behavior of a double—gate (DG) TFET is presented. However, simplicity and flexibility of the model allow to use it for other type of TFET structures such as single—gate (SG) planar or nanowire TFETs. The model is verified with the TCAD simulations as well as the measurement data of fabricated TFETs. The capacitance model also includes the effect of the parasitic elements. Furthermore, in the context of this work also the influence of Schottky barrier contacts on the capacitive behavior of TFETs is investigated. This model is finally combined with an existing compact DC model to form a complete compact TFET model. The compact model is then implemented for transient simulations of TFET—based inverter and ring—oscillator circuits

Charge Trap Memory Based on Few-Layered Black Phosphorus

Atomically thin layered two-dimensional materials, including transition-metal dichacolgenide (TMDC) and black phosphorus (BP), (1) have been receiving much attention, because of their promising physical properties and potential applications in flexible and transparent electronic devices . Here, for the first time we show non-volatile chargetrap memory devices, based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3 /HfO2 /Al2O3 charge-trap gate stack. An unprecedented memory window exceeding 12 V is observed, due to the extraordinary trapping ability of HfO2. The device shows a high endurance and a stable retention of ?25% charge loss after 10 years, even drastically lower than reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards the flexible and transparent memory devices utilising atomically thin two-dimensional materials. The combination of 2D materials with traditional high-k charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.Comment: 16 pages, 10 figures, 1 table. arXiv admin note: substantial text overlap with arXiv:1407.7432 by other authors; text overlap with arXiv:1505.04859 by other authors without attributio

Self-powered Time-Keeping and Time-of-Occurrence Sensing

Self-powered and passive Internet-of-Things (IoT) devices (e.g. RFID tags, financial assets, wireless sensors and surface-mount devices) have been widely deployed in our everyday and industrial applications. While diverse functionalities have been implemented in passive systems, the lack of a reference clock limits the design space of such devices used for applications such as time-stamping sensing, recording and dynamic authentication. Self-powered time-keeping in passive systems has been challenging because they do not have access to continuous power sources. While energy transducers can harvest power from ambient environment, the intermittent power cannot support continuous operation for reference clocks. The thesis of this dissertation is to implement self-powered time-keeping devices on standard CMOS processes. In this dissertation, a novel device that combines the physics of quantum tunneling and floating-gate (FG) structures is proposed for self-powered time-keeping in CMOS process. The proposed device is based on thermally assisted Fowler-Nordheim (FN) tunneling process across high-quality oxide layer to discharge the floating-gate node, therefore resulting in a time-dependent FG potential. The device was fully characterized in this dissertation, and it does not require external powering during runtime, making it feasible for passive devices and systems. Dynamic signature based on the synchronization and desynchronization behavior of the FN timer is proposed for authentication of IoT devices. The self-compensating physics ensure that when distributed timers are subjected to identical environment variances that are common-mode noise, they can maintain synchronization with respect to each other. On the contrary, different environment conditions will desynchronize the timers creating unique signatures. The signatures could be used to differentiate between products that belong to different supply-chains or products that were subjected to malicious tampering. SecureID type dynamic authentication protocols based on the signature generated by the FN timers are proposed and they are proven to be robust to most attacks. The protocols are further analyzed to be lightweight enough for passive devices whose computational sources are limited. The device could also be applied for self-powered sensing of time-of-occurrence. The prototype was verified by integrating the device with a self-powered mechanical sensor to sense and record time-of-occurrence of mechanical events. The system-on-chip design uses the timer output to modulate a linear injector to stamp the time information into the sensing results. Time-of-occurrence can be reconstructed by training the mathematical model and then applying that to the test data. The design was verified to have a high reconstruction accuracy

Tunnel Field-Effect Transistor: Impact of the Asymmetric and Symmetric Ambipolarity on Fault and Performance in Digital Circuits

Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room temperature holding for the MOSFET technologies. Nevertheless, TFET technology still suffers of ambipolar conduction, limiting its applicability in digital systems. In this work, we analyze through SPICE simulations, the impact of the symmetric and asymmetric ambipolarity in failure and power consumption for TFET-based complementary logic circuits. Our results clarify the circuit-level effects induced by the ambipolarity feature, demonstrating that it affects the correct functioning of logic gates and strongly impacts power consumption. We believe that our outcomes motivate further research towards technological solutions for ambipolarity suppression in TFET technology for near-future ultra-low-power application

A Study of Ozone as an Oxygen Source for the Growth of High-Κ Dielectric Films for Gate Dielectric on GaN/AlGaN/GaN

GaN is a promising alternative to silicon technology for the next-generation high-power and high-frequency electronics. The choice stems from the intrinsic properties of GaN of a wide bandgap and consequently high breakdown voltage, high saturation electron velocity and good thermal conductivity. Spontaneous and piezoelectric polarization effects cause accumulation of a high density of carriers at III-Nitride heterointerfaces enabling engineering of high mobility channels. The primary factor inhibiting the further growth of GaN HEMTs is the high leakage current leading to device unreliability. The MIS-structure used in Si-CMOS processing has been adapted and shown to reduce leakage current in GaN technology. However, the introduction of an insulator adds another interface which suffers from poor quality due to innumerable traps with varying time constants. This leads to device threshold voltage instability and drain current collapse, while decreasing the device transconductance due to the increased gate-to-channel spatial separation. High-K dielectrics have been shown to reduce leakage current with smaller decrease in transconductance in Si-CMOS technology and therefore, applied to GaN technology. ALD is recognized as a novel method for high-κ gate dielectric deposition, where H2O is primarily used as the oxygen source for growth; excellent properties have been reported. However, ozone-grown films show further suppressed leakage current and offer better interfacial quality on silicon. In this study, MOSCaps have been developed on GaN/AlGaN/GaN heterostructures with PECVD Si3N4 and ALD HfO2 as the passivation layer and gate dielectric, respectively. HfO2 was grown using either H2O or ozone as the oxygen source. XPS analysis, capacitance-voltage, conductance-voltage and leakage current-voltage characteristics have been used as probes to study the quality of the film and its interface with the III-N semiconductor. It is observed that due to the sufficient supply of oxygen, ozone helps in the formation of a better bulk dielectric by more complete oxidation. However, the interface is degraded by uncontrolled surface oxidation of the barrier layer or/and penetration of oxygen impurities, creating shallow donor traps aiding in leakage. The overall leakage current with the ozone-grown dielectric is reduced by almost half-an-order of magnitude due to the better bulk dielectric achieved

Design and Evaluation of a Sub-1-Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process

Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI), Fowler-Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the oating-gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented. Fabrication of ash memory in a standard CMOS process presents significant design challenges. The absence of multiple polysilicon layers requires that additional devices be used to control the oating-gate voltage. Furthermore high-voltage devices are often required to isolate the selected memory cells during write and erase cycles. However, a single-poly design allows portability to another standard process provided that the oating-gate characteristics are known. A ash memory system is presented here that has been fabricated in a standard 130 nanometer CMOS process. The design utilizes capacitive feedback to maintain desired injection current during programming. It also includes a sense amplifier design which features auto-zeroing of inherent offsets. Comparisons to existing memory designs show that a significant improvement in areal density was achieved through the elimination of on-die high-voltage charge pumps and switches. Measurements were performed over a range of clock frequencies and supply voltages. Results show that this memory system is capable of a read access time of 3.5 microseconds with a 1 megahertz clock while consuming less than 25 microwatts from a 1 volt supply. Operation down to 650 millivolts was confirmed where power consumption was reduced to only 3.4 microwatts. The low power consumption and high density of this ash memory make it an excellent choice for on-die firmware storage in battery-powered embedded applications

Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design

The driving engine for the exponential growth of digital information processing systems is scaling down the transistor dimensions. For decades, this has enhanced the device performance and density. However, the International Technology Roadmap for Semiconductors (ITRS) states the end of Moore’s law in the next decade due to the scaling challenges of silicon-based CMOS electronics, e.g. extremely high power density. The forward-looking solutions are the utilization of emerging materials and devices for integrated circuits. The Ph.D. dissertation focuses on graphene, one atomic layer of carbon sheet, experimentally discovered in 2004. Since fabrication technology of emerging materials is still in early stages, transistor modeling has been playing an important role for evaluating futuristic graphene-based devices and circuits. The GNR FET has been simulated by solving a numerical quantum transport model based on self-consistent solution of the 3D Poisson equation and 1D Schrödinger equations within the non-equilibrium Green’s function (NEGF) formalism. The quantum transport model fully treats short channel-length electrostatic effects and the quantum tunneling effects, leading to the technology exploration of graphene nanoribbon field effect transistors (GNRFETs) for the future. A comprehensive study of static metrics and switching attributes of GNRFET has been presented including the performance dependence of device characteristics to the GNR width and the scaling of its channel length down to 2.5 nanometer. It has been found that increasing the GNR width deteriorate the off-state performance of the GNRFET, such that, narrower armchair GNRs improved the device robustness to short channel effects, leading to better off-state performance considering smaller off-current, larger ION/IOFF ratio, smaller subthreshold swing and smaller drain-induced barrier-lowering. The wider armchair GNRs allow the scaling of channel length and supply voltage resulting in better on-state performance such as higher drive current, smaller intrinsic gate-delay time and smaller power-delay product. In addition, the width-dependent characteristics of GNR FETs is investigated for two GNR semiconducting families (3p,0) and (3p+1,0). It has been found that the GNRs(3p+1,0) demonstrates superior off-state performance, while, on the other hand, GNRs(3p,0) shows superior on-state performance. Thus, GNRs(3p+1,0) are promising for low-power design, while GNRs(3p,0) indicate a more preferable attribute for high frequency applications