3,184 research outputs found

    Agile Calibration Process of Full-Stack Simulation Frameworks for V2X Communications

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    Computer simulations and real-world car trials are essential to investigate the performance of Vehicle-to-Everything (V2X) networks. However, simulations are imperfect models of the physical reality and can be trusted only when they indicate agreement with the real-world. On the other hand, trials lack reproducibility and are subject to uncertainties and errors. In this paper, we will illustrate a case study where the interrelationship between trials, simulation, and the reality-of-interest is presented. Results are then compared in a holistic fashion. Our study will describe the procedure followed to macroscopically calibrate a full-stack network simulator to conduct high-fidelity full-stack computer simulations.Comment: To appear in IEEE VNC 2017, Torino, I

    A Statistical STT-RAM Design View and Robust Designs at Scaled Technologies

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    Rapidly increased demands for memory in electronic industry and the significant technical scaling challenges of all conventional memory technologies motivated the researches on the next generation memory technology. As one promising candidate, spin-transfer torque random access memory (STT-RAM) features fast access time, high density, non-volatility, and good CMOS process compatibility. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous increasing of tunnel magneto-resistance(TMR) ratio of the MTJ inspires the development of multi-level cell (MLC) STT-RAM, which allows multiple data bits be stored in a single memory cell. Two types of MLC STT-RAM cells, namely, parallel MLC and series MLC, were also proposed. However, like all other nanoscale devices, the performance and reliability of STT-RAM cells are severely affected by process variations, intrinsic device operating uncertainties and environmental fluctuations. The storage margin of a MLC STT-RAM cell, i.e., the distinction between the lowest and highest resistance states, is partitioned into multiple segments for multi-level data representation. As a result, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations and the thermal-induced randomness of MTJ switching. In this work, we systematically analyze the impacts of CMOS and MTJ process variations, MTJ resistance switching randomness that induced by intrinsic thermal fluctuations, and working temperature changes on STT-RAM cell designs. The STT-RAM cell reliability issues in both read and write operations are first investigated. A combined circuit and magnetic simulation platform is then established to quantitatively study the persistent and non-persistent errors in STT-RAM cell operations. Then, we analyzed the extension of STT-RAM cell behaviors from SLC (single-level- cell) to MLC (multi-level- cell). On top of that, we also discuss the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the MLC STT-RAM cells from statistical design perspective. Our simulation results show that under the current available technology, series MLC STT-RAM demonstrates overwhelming benefits in the read and write reliability compared to parallel MLC STT-RAM and could potentially satisfy the requirement of commercial practices. Finally, with the detail analysis study of STT-RAM cells, we proposed several error reduction design, such as ADAMS structure, and FA-STT structure

    Extensive X-ray variability studies of NGC 7314 using long XMM-Newton observations

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    We present a detailed X-ray variability study of the low mass Active Galactic Nuclei (AGN) NGC 7314 using the two newly obtained XMM-Newton observations (140140 and 130130 ks), together with two archival data sets of shorter duration (4545 and 8484 ks). The relationship between the X-ray variability characteristics and other physical source properties (such as the black hole mass) are still relatively poorly defined, especially for low-mass AGN. We perform a new, fully analytical, power spectral density (PSD) model analysis method, which will be described in detail in a forthcoming paper, that takes into consideration the spectral distortions, caused by red-noise leak. We find that the PSD in the 0.5100.5-10 keV energy range, can be represented by a bending power-law with a bend around 6.7×1056.7\times10^{-5} Hz, having a slope of 0.510.51 and 1.991.99 below and above the bend, respectively. Adding our bend time-scale estimate, to an already published ensemble of estimates from several AGN, supports the idea that the bend time-scale depends linearly only on the black hole mass and not on the bolometric luminosity. Moreover, we find that as the energy range increases, the PSD normalization increases and there is a hint that simultaneously the high frequency slope becomes steeper. Finally, the X-ray time-lag spectrum of NGC 7314 shows some very weak signatures of relativistic reflection, and the energy resolved time-lag spectrum, for frequencies around 3×1043\times10^{-4} Hz, shows no signatures of X-ray reverberation. We show that the previous claim about ks time-delays in this source, is simply an artefact induced by the minuscule number of points entering during the time-lag estimation in the low frequency part of the time-lag spectrum (i.e. below 10410^{-4} Hz).Comment: Accepted for publication in MNRAS. The paper is 21 pages long and contains 15 figures and 3 table

    ECFA Detector R&D Panel, Review Report

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    Two special calorimeters are foreseen for the instrumentation of the very forward region of an ILC or CLIC detector; a luminometer (LumiCal) designed to measure the rate of low angle Bhabha scattering events with a precision better than 103^{-3} at the ILC and 102^{-2} at CLIC, and a low polar-angle calorimeter (BeamCal). The latter will be hit by a large amount of beamstrahlung remnants. The intensity and the spatial shape of these depositions will provide a fast luminosity estimate, as well as determination of beam parameters. The sensors of this calorimeter must be radiation-hard. Both devices will improve the e.m. hermeticity of the detector in the search for new particles. Finely segmented and very compact electromagnetic calorimeters will match these requirements. Due to the high occupancy, fast front-end electronics will be needed. Monte Carlo studies were performed to investigate the impact of beam-beam interactions and physics background processes on the luminosity measurement, and of beamstrahlung on the performance of BeamCal, as well as to optimise the design of both calorimeters. Dedicated sensors, front-end and ADC ASICs have been designed for the ILC and prototypes are available. Prototypes of sensor planes fully assembled with readout electronics have been studied in electron beams.Comment: 61 pages, 51 figure

    Custom Integrated Circuits

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    Contains reports on four research projects.U.S. Air Force - Office of Scientific Research (Contract F49620-81-C-0054)U.S. Air Force - Office of Scientific Research (Contract F49620-84-C-0004)National Science Foundation (Grant ECS81-18160)National Science Foundation (Grant ECS83-10941

    Physical Investigation into Effective Voltage Balancing by Temporary Clamp Technique for the Series Connection of IGBTs

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    The series connection of IGBTs is essential for high-voltage applications where fast switching performances need to be maintained. However, unbalanced voltage sharing is a major resistance to the converter application of this structure. There are a number of causes leading to voltage unbalance, such as different signal delays, parasitic parameters, tail currents, and so on. A temporary clamp scheme performed by active voltage control (AVC) has been proven to be effective in solving the unbalanced voltage-sharing issue. However, the basic physics has not been investigated. In this paper, the physical principle of voltage unbalance within IGBTs series operation is discussed. The carrier storage region differences are concluded to be the intrinsic cause of unbalanced voltage sharing. By using an accurate Fourier-series-based IGBT simulation model with appropriate assumptions, a physical explanation for temporary clamp is provided in detail. At the end of the tail current period when the excess carrier concentration becomes close to the intrinsic doping density, the temporary clamp is able to achieve satisfactory equal voltage sharing

    Electronic Structure Shift of Deep Nanoscale Silicon by SiO2_2- vs. Si3_3N4_4-Embedding as Alternative to Impurity Doping

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    Conventional impurity doping of deep nanoscale silicon (dns-Si) used in ultra large scale integration (ULSI) faces serious challenges below the 14 nm technology node. We report on a new fundamental effect in theory and experiment, namely the electronic structure of dns-Si experiencing energy offsets of ca. 1 eV as a function of SiO2_2- vs. Si3_3N4_4-embedding with a few monolayers (MLs). An interface charge transfer (ICT) from dns-Si specific to the anion type of the dielectric is at the core of this effect and arguably nested in quantum-chemical properties of oxygen (O) and nitrogen (N) vs. Si. We investigate the size up to which this energy offset defines the electronic structure of dns-Si by density functional theory (DFT), considering interface orientation, embedding layer thickness, and approximants featuring two Si nanocrystals (NCs); one embedded in SiO2_2 and the other in Si3_3N4_4. Working with synchrotron ultraviolet photoelectron spectroscopy (UPS), we use SiO2_2- vs. Si3_3N4_4-embedded Si nanowells (NWells) to obtain their energy of the top valence band states. These results confirm our theoretical findings and gauge an analytic model for projecting maximum dns-Si sizes for NCs, nanowires (NWires) and NWells where the energy offset reaches full scale, yielding to a clear preference for electrons or holes as majority carriers in dns-Si. Our findings can replace impurity doping for n/p-type dns-Si as used in ultra-low power electronics and ULSI, eliminating dopant-related issues such as inelastic carrier scattering, thermal ionization, clustering, out-diffusion and defect generation. As far as majority carrier preference is concerned, the elimination of those issues effectively shifts the lower size limit of Si-based ULSI devices to the crystalization limit of Si of ca. 1.5 nm and enables them to work also under cryogenic conditions.Comment: 14 pages, 17 Figures with a total 44 graph

    Nanoelectronic COupled problems solutions - nanoCOPS: modelling, multirate, model order reduction, uncertainty quantification, fast fault simulation

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    The FP7 project nanoCOPS derives new methods for simulation during development of designs of integrated products. It covers advanced simulation techniques for electromagnetics with feedback couplings to electronic circuits, heat and stress. It is inspired by interest from semiconductor industry and by a simulation tool vendor in electronic design automation. The project is on-going and the paper presents the outcomes achieved after the first half of the project duration
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