Broadband quadrature-squeezed vacuum and nonclassical photon number correlations from a nanophotonic device

We report the first demonstrations of both quadrature squeezed vacuum and photon number difference squeezing generated in an integrated nanophotonic device. Squeezed light is generated via strongly driven spontaneous four-wave mixing below threshold in silicon nitride microring resonators. The generated light is characterized with both homodyne detection and direct measurements of photon statistics using photon number-resolving transition edge sensors. We measure $1.0(1)$~dB of broadband quadrature squeezing (${\sim}4$~dB inferred on-chip) and $1.5(3)$~dB of photon number difference squeezing (${\sim}7$~dB inferred on-chip). Nearly-single temporal mode operation is achieved, with raw unheralded second-order correlations $g^{(2)}$ as high as $1.87(1)$ measured (${\sim}1.9$~when corrected for noise). Multi-photon events of over 10 photons are directly detected with rates exceeding any previous quantum optical demonstration using integrated nanophotonics. These results will have an enabling impact on scaling continuous variable quantum technology.Comment: Significant improvements and updates to photon number squeezing results and discussions, including results on single temporal mode operatio

고속 DRAM 인터페이스를 위한 전압 및 온도에 둔감한 클록 패스와 위상 오류 교정기 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.To cope with problems caused by the high-speed operation of the dynamic random access memory (DRAM) interface, several approaches are proposed that are focused on the clock path of the DRAM. Two delay-locked loop (DLL) based schemes, a forwarded-clock (FC) receiver (RX) with self-tracking loop and a quadrature error corrector, are proposed. Moreover, an open-loop based scheme is presented for drift compensation in the clock distribution. The open-loop scheme consumes less power consumption and reduces design complexity. The FC RX uses DLLs to compensate for voltage and temperature (VT) drift in unmatched memory interfaces. The self-tracking loop consists of two-stage cascaded DLLs to operate in a DRAM environment. With the write training and the proposed DLL, the timing relationship between the data and the sampling clock is always optimal. The proposed scheme compensates for delay drift without relying on data transitions or re-training. The proposed FC RX is fabricated in 65-nm CMOS process and has an active area containing 4 data lanes of 0.0329 mm2. After the write training is completed at the supply voltage of 1 V, the measured timing margin remains larger than 0.31-unit interval (UI) when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC RX achieves an energy efficiency of 0.45 pJ/bit. Contrary to the aforementioned scheme, an open-loop-based voltage drift compensation method is proposed to minimize power consumption and occupied area. The overall clock distribution is composed of a current mode logic (CML) path and a CMOS path. In the proposed scheme, the architecture of the CML-to-CMOS converter (C2C) and the inverter is changed to compensate for supply voltage drift. The bias generator provides bias voltages to the C2C and inverters according to supply voltage for delay adjustment. The proposed clock tree is fabricated in 40 nm CMOS process and the active area is 0.004 mm2. When the supply voltage is modulated by a sinusoidal wave with 1 MHz, 100 mV peak-to-peak swing from the center of 1.1 V, applying the proposed scheme reduces the measured root-mean-square (RMS) jitter from 3.77 psRMS to 1.61 psRMS. At 6 GHz output clock, the power consumption of the proposed scheme is 11.02 mW. A DLL-based quadrature error corrector (QEC) with a wide correction range is proposed for the DRAM whose clocks are distributed over several millimeters. The quadrature error is corrected by adjusting delay lines using information from the phase error detector. The proposed error correction method minimizes increased jitter due to phase error correction by setting at least one of the delay lines in the quadrature clock path to the minimum delay. In addition, the asynchronous calibration on-off scheme reduces power consumption after calibration is complete. The proposed QEC is fabricated in 40 nm CMOS process and has an active area of 0.048 mm2. The proposed QEC exhibits a wide correctable error range of 101.6 ps and the remaining phase errors are less than 2.18° from 0.8 GHz to 2.3 GHz clock. At 2.3 GHz, the QEC contributes 0.53 psRMS jitter. Also, at 2.3 GHz, the power consumption is reduced from 8.89 mW to 3.39 mW when the calibration is off.본 논문에서는 동적 랜덤 액세스 메모리 (DRAM)의 속도가 증가함에 따라 클록 패스에서 발생할 수 있는 문제에 대처하기 위한 세 가지 회로들을 제안하였다. 제안한 회로들 중 두 방식들은 지연동기루프 (delay-locked loop) 방식을 사용하였고 나머지 한 방식은 면적과 전력 소모를 줄이기 위해 오픈 루프 방식을 사용하였다. DRAM의 비정합 수신기 구조에서 데이터 패스와 클록 패스 간의 지연 불일치로 인해 전압 및 온도 변화에 따라 셋업 타임 및 홀드 타임이 줄어드는 문제를 해결하기 위해 지연동기루프를 사용하였다. 제안한 지연동기루프 회로는 DRAM 환경에서 동작하도록 두 개의 지연동기루프로 나누었다. 또한 초기 쓰기 훈련을 통해 데이터와 클록을 타이밍 마진 관점에서 최적의 위치에 둘 수 있다. 따라서 제안하는 방식은 데이터 천이 정보가 필요하지 않다. 65-nm CMOS 공정을 이용하여 만들어진 칩은 6.4 Gb/s에서 0.45 pJ/bit의 에너지 효율을 가진다. 또한 1 V에서 쓰기 훈련 및 지연동기루프를 고정시키고 0.94 V에서 1.06 V까지 공급 전압이 바뀌었을 때 타이밍 마진은 0.31 UI보다 큰 값을 유지하였다. 다음으로 제안하는 회로는 클록 분포 트리에서 전압 변화로 인해 클록 패스의 지연이 달라지는 것을 앞서 제시한 방식과 달리 오픈 루프 방식으로 보상하였다. 기존 클록 패스의 인버터와 CML-to-CMOS 변환기의 구조를 변경하여 바이어스 생성 회로에서 생성한 공급 전압에 따라 바뀌는 바이어스 전압을 가지고 지연을 조절할 수 있게 하였다. 40-nm CMOS 공정을 이용하여 만들어진 칩의 6 GHz 클록에서의 전력 소모는 11.02 mW로 측정되었다. 1.1 V 중심으로 1 MHz, 100 mV 피크 투 피크를 가지는 사인파 성분으로 공급 전압을 변조하였을 때 제안한 방식에서의 지터는 기존 방식의 3.77 psRMS에서 1.61 psRMS로 줄어들었다. DRAM의 송신기 구조에서 다중 위상 클록 간의 위상 오차는 송신된 데이터의 데이터 유효 창을 감소시킨다. 이를 해결하기 위해 지연동기루프를 도입하게 되면 증가된 지연으로 인해 위상이 교정된 클록에서 지터가 증가한다. 본 논문에서는 증가된 지터를 최소화하기 위해 위상 교정으로 인해 증가된 지연을 최소화하는 위상 교정 회로를 제시하였다. 또한 유휴 상태에서 전력 소모를 줄이기 위해 위상 오차를 교정하는 회로를 입력 클록과 비동기식으로 끌 수 있는 방법 또한 제안하였다. 40-nm CMOS 공정을 이용하여 만들어진 칩의 위상 교정 범위는 101.6 ps이고 0.8 GHz 부터 2.3 GHz까지의 동작 주파수 범위에서 위상 교정기의 출력 클록의 위상 오차는 2.18°보다 작다. 제안하는 위상 교정 회로로 인해 추가된 지터는 2.3 GHz에서 0.53 psRMS이고 교정 회로를 껐을 때 전력 소모는 교정 회로가 켜졌을 때인 8.89 mW에서 3.39 mW로 줄어들었다.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Background on DRAM Interface 5 2.1 Overview 5 2.2 Memory Interface 7 Chapter 3 Background on DLL 11 3.1 Overview 11 3.2 Building Blocks 15 3.2.1 Delay Line 15 3.2.2 Phase Detector 17 3.2.3 Charge Pump 19 3.2.4 Loop filter 20 Chapter 4 Forwarded-Clock Receiver with DLL-based Self-tracking Loop for Unmatched Memory Interfaces 21 4.1 Overview 21 4.2 Proposed Separated DLL 25 4.2.1 Operation of the Proposed Separated DLL 27 4.2.2 Operation of the Digital Loop Filter in DLL 31 4.3 Circuit Implementation 33 4.4 Measurement Results 37 4.4.1 Measurement Setup and Sequence 38 4.4.2 VT Drift Measurement and Simulation 40 Chapter 5 Open-loop-based Voltage Drift Compensation in Clock Distribution 46 5.1 Overview 46 5.2 Prior Works 50 5.3 Voltage Drift Compensation Method 52 5.4 Circuit Implementation 57 5.5 Measurement Results 61 Chapter 6 Quadrature Error Corrector with Minimum Total Delay Tracking 68 6.1 Overview 68 6.2 Prior Works 70 6.3 Quadrature Error Correction Method 73 6.4 Circuit Implementation 82 6.5 Measurement Results 88 Chapter 7 Conclusion 96 Bibliography 98 초록 102Docto

Advanced digital modulation: Communication techniques and monolithic GaAs technology

Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case

Hardware simulation of KU-band spacecraft receiver and bit synchronizer, phase 2, volume 1

The acquisition behavior of the PN subsystem of an automatically acquiring spacecraft receiver was studied. A symbol synchronizer subsystem was constructed and integrated into the composite simulation of the receiver. The overall performance of the receiver when subjected to anomalies such as signal fades was evaluated. Potential problems associated with PN/carrier sweep interactions were investigated

Implementation of a Software Defined Spread Spectrum Communication System

The goal of this thesis is to develop a framework to prototype a software defined direct sequence spread spectrum transceiver that can be used as a node in an ad hoc network. We introduce the concept of a software radio, the current state of art, and GNU Radio and its concepts. We discuss in detail the design and development methods of GNU Radio and develop a flowgraph in Python to demonstrate the method of development. We present a mathematical analysis of (DSSS) modulation and demodulation schemes along with the transmitter and receiver design. We use this design to develop an analogous design in GNU Radio using the signal processing blocks that are present in GNU Radio and ones we develop. We perform simulations and tests to validate the algorithms, signal processing blocks and flowgraphs that we developed. We find that the signal acquistion algorithm is capable of determining the code and frequency offset in a received (DSSS) signal. We also find that the carrier tracking loop is capable of tracking the received carrier when the signal has a high (SNR). We conclude that GNU Radio as a technology can be used to prototype transceivers that are highly configurable and expandable. Finally, we identify and suggest some possible areas where this design can be developed and improved further

All-semiconductor High Power Mode-locked Laser System

All-optical synchronization and its application in advanced optical communications have been investigated in this dissertation. Dynamics of all-optical timing synchronization (clock recovery) using multi-section gain-coupled distributed-feedback (MS-GC DFB) lasers are discussed. A record speed of 180-GHz timing synchronization has been demonstrated using this device. An all-optical carrier synchronization (phase and polarization recovery) scheme from PSK (phase shift keying) data is proposed and demonstrated for the first time. As an application of all-optical synchronization, the characterization of advanced modulation formats using a linear optical sampling technique was studied. The full characterization of 10-Gb/s RZ-BPSK (return-to-zero binary PSK) data has been demonstrated. Fast lockup and walk-off of the all-optical timing synchronization process on the order of nanoseconds were measured in both simulation and experiment. Phase stability of the recovered clock from a pseudo-random bit sequence signal can be achieved by limiting the detuning between the frequency of free-running self-pulsation and the input bit rate. The simulation results show that all-optical clock recovery using TS-DFB lasers can maintain a better than 5 % clock phase stability for large variations in power, bit rate and optical carrier frequency of the input data and therefore is suitable for applications in ultrafast optical packet switching. All-optical timing synchronization of 180-Gb/s data streams has been demonstrated using a MS-GC DFB laser. The recovered clock has a jitter of less than 410 fs over a dynamic range of 7 dB. All-optical carrier synchronization from phase modulated data utilizes a phase sensitive oscillator (PSO), which used a phase sensitive amplifier (PSA) as a gain block. Furthermore, all-optical carrier synchronization from 10-Gb/s BPSK data was demonstrated in experiment. The PSA is configured as a nonlinear optical loop mirror (NOLM). A discrete linear system analysis was carried out to understand the stability of the PSO. Complex envelope measurement using coherent linear optical sampling with mode-locked sources is investigated. It is shown that reliable measurement of the phase requires that one of the optical modes of the sampling pulses be locked to the optical carrier of the data signal to be measured. Carrier-envelope offset (CEO) is found to have a negligible effect on the measurement. Measurement errors of the intensity profile and phase depend on the pulsewidth and chirp of the sampling pulses as well as the detuning between the carrier frequencies of the data signal and the center frequency of the sampling source. Characterization of the 10-Gb/s RZ-BPSK signal was demonstrated using the coherent detection technique. Measurements of the optical intensity profile, chirp and constellation diagram were demonstrated. A CW local oscillator was used and electrical sampling was performed using a sampling scope. A novel feedback scheme was used to stabilize homodyne detection

Dispersions of ellipsoidal particles in a nematic liquid crystal

Colloidal particles dispersed in a partially ordered medium, such as a liquid crystal (LC) phase, disturb its alignment and are subject to elastic forces. These forces are long-ranged, anisotropic and tunable through temperature or external fields, making them a valuable asset to control colloidal assembly. The latter is very sensitive to the particle geometry since it alters the interactions between the colloids. We here present a detailed numerical analysis of the energetics of elongated objects, namely prolate ellipsoids, immersed in a nematic host. The results, complemented with qualitative experiments, reveal novel LC configurations with peculiar topological properties around the ellipsoids, depending on their aspect ratio and the boundary conditions imposed on the nematic order parameter. The latter also determine the preferred orientation of ellipsoids in the nematic field, because of elastic torques, as well as the morphology of particles aggregates.Comment: 31 pages, 11 figure

Assessing the Spoofing Threat: Development of a Portable GPS Civilian Spoofer

A portable civilian GPS spoofer is implemented on a digital signal processor and used to characterize spoofing effects and develop defenses against civilian spoofing. This work is intended to equip GNSS users and receiver manufacturers with authentication methods that are effective against unsophisticated spoofing attacks. The work also serves to refine the civilian spoofing threat assessment by demonstrating the challenges involved in mounting a spoofing attack.Aerospace Engineering and Engineering Mechanic

Hardware simulation of Ku-band spacecraft receiver and bit synchronizer, volume 1

A hardware simulation which emulates an automatically acquiring transmit receive spread spectrum communication and tracking system and developed for use in future NASA programs involving digital communications is considered. The system architecture and tradeoff analysis that led to the selection of the system to be simulated is presented