ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

380 MHz Low-Power Sharp-Rejection Active-RC LPF for IEEE 802.15.4a UWB WPAN

This paper describes a wide-band sharp-rejection active-RC low pass filter (LPF) for pulse-based UWB IEEE 802.15.4a WPA, applications. Sharp rejection is attributed to the combination of different AC characteristic of three biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency performance for the designed filter. The LPF is designed in 0.13μm TSMC CMOS process. The cutoff frequency is 380MHz with about 50% of the tuning range from 300-500MHz. The rejection is 40 dB at 600 MHz. The passband ripple is less than 1.5dB and the filter consumes 4.6mA from 1.2V supply. Core chip size is 580 x 700μm2

380 MHz Low-Power Sharp-Rejection Active-RC LPF for IEEE 802.15.4a UWB WPAN

This paper describes a wide-band sharp-rejection active-RC low pass filter (LPF) for pulse-based UWB IEEE 802.15.4a WPA, applications. Sharp rejection is attributed to the combination of different AC characteristic of three biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency performance for the designed filter. The LPF is designed in 0.13μm TSMC CMOS process. The cutoff frequency is 380MHz with about 50% of the tuning range from 300-500MHz. The rejection is 40 dB at 600 MHz. The passband ripple is less than 1.5dB and the filter consumes 4.6mA from 1.2V supply. Core chip size is 580 x 700μm2

Polyphase filter with parametric tuning

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 201

A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

Design for testability of high-order OTA-C filters

Copyright © 2016 John Wiley & Sons, Ltd.A study of oscillation-based test for high-order Operational Transconductance Amplifier-C (OTA-C) filters is presented. The method is based on partition of a high-order filter into second-order filter functions. The opening Q-loop and adding positive feedback techniques are developed to convert the second-order filter section into a quadrature oscillator. These techniques are based on an open-loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth-order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth-order cascade, inverse follow-the-leader feedback (IFLF) and LF OTA-C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation-based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA-C filters, respectively. Copyright ÂPeer reviewe

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

Two Senior Projects: 2.4 GHz, 40% Efficiency Radio Frequency Amplifier, IEEE Design Contest, & Design and Implementation of a Software Costas Loop for Audio Frequencies

How to Read this Document: This document combines two senior project reports. The first senior project documents designing a class AB RF amplifier. The second, discusses the design and implementation of a software Costas loop for audio frequencies. The first report begins on the next page, while the Costas loop report starts on page 24. The two reports are orthogonal from one another. It is not a prerequisite to read the RF amplifier report before reading the Costas loop report. This document is merely two reports combined into one document. The second report, about the Costas loop, was written as a replacement to the first. However, it was decided, to include the first senior project, in order to make available information and insights that were encountered during the RF amplifier design and construction process, that someone else might find helpful. RF Amplifier Abstract: In this senior project, a 4W 2.4 GHz power amplifier (PA) is designed as an entry for IEEE s high frequency amplifier design contest. The design uses Cree s CGH40010F Gallium Nitride (GaN) transistor, because it is capable of outputting 10W up to 6 GHz. Cree also provides simulation models for the Agilent Design System (ADS) the RF design software used to design this PA. In order to maximize both efficiency and linearity, the PA is class AB biased. Matching networks are implemented on FR4 substrate. Tuning the gate voltage on the final design minimizes intermodulation distortion (IMD) and improves linearity. The final design exhibits 40% power added efficiency (PAE) and greater than 20 dBc IMD within a 5 MHz bandwidth. Software Costas Loop Abstract: A Costas loop is implemented in software with Python. A small-signal linear model is derived in order to determine loop stability. An interactive program was developed to tune loop parameters in order to obtain critically damped step response. The effect of lowpass filter phase delay on stability is discussed