Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies

Detection of Malicious Circuitry using Transition Probability Based Node Reduction Technique

In recent years, serious concerns have been raised against the tampering of integrated circuits due to outsourcing of circuits for fabrication. It has led to the addition of malicious circuitry known as Hardware Trojan. In this paper, a transition probability based node reduction technique for faster and efficient Hardware Trojan (HT) detection has been attempted. In the proposed method, the fact that the least controllable and observable nodes or the nodes with least transition probability are more vulnerable as Trojan sites is taken into consideration. The nodes that have lesser activity than the threshold are the candidate nodes. At each candidate node, segmentation is done for further leakage power analysis to detect the presence of Trojans. Experimental results observed on ISCAS’85 and ISCAS’89 benchmark circuits illustrate that the proposed work can achieve remarkable node reduction upto 78.81% and time reduction upto 58.7%. It was also observed that the circuit activity can be increased by varying the input probability. Hence, for further reduction in the Trojan activation time, the weighted input probability was obtained

A Touch of Evil: High-Assurance Cryptographic Hardware from Untrusted Components

The semiconductor industry is fully globalized and integrated circuits (ICs) are commonly defined, designed and fabricated in different premises across the world. This reduces production costs, but also exposes ICs to supply chain attacks, where insiders introduce malicious circuitry into the final products. Additionally, despite extensive post-fabrication testing, it is not uncommon for ICs with subtle fabrication errors to make it into production systems. While many systems may be able to tolerate a few byzantine components, this is not the case for cryptographic hardware, storing and computing on confidential data. For this reason, many error and backdoor detection techniques have been proposed over the years. So far all attempts have been either quickly circumvented, or come with unrealistically high manufacturing costs and complexity. This paper proposes Myst, a practical high-assurance architecture, that uses commercial off-the-shelf (COTS) hardware, and provides strong security guarantees, even in the presence of multiple malicious or faulty components. The key idea is to combine protective-redundancy with modern threshold cryptographic techniques to build a system tolerant to hardware trojans and errors. To evaluate our design, we build a Hardware Security Module that provides the highest level of assurance possible with COTS components. Specifically, we employ more than a hundred COTS secure crypto-coprocessors, verified to FIPS140-2 Level 4 tamper-resistance standards, and use them to realize high-confidentiality random number generation, key derivation, public key decryption and signing. Our experiments show a reasonable computational overhead (less than 1% for both Decryption and Signing) and an exponential increase in backdoor-tolerance as more ICs are added

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness

Manifestation and mitigation of node misbehaviour in adhoc networks

Mobile adhoc network is signified as a boon for advance and future wireless communication system. Owing to its self-establishing network features and decentralization, the system can actually establish a wireless communication with vast range of connectivity with the other nodes. However, the system of MANET is also beheld with various technical impediments owing to its inherent dynamic topologies. Although there are abundant volume of research work, but very few have been able to effectively address the node misbehavior problems in MANET. The paper initially tries to draw a line between different types of nodes in MANETs based on their behavior characteristics, then reviews some of the significant contribution of the prior researches for addressing node misbehavior issues. A major emphasis is laid on is the researches which use game theory as a tool to study and address the misbehavior problems. The manuscript is developed considering some of the latest and standard evidences of past 5 years and finally discusses the open issues related to the problems

A Primer on Architectural Level Fault Tolerance

This paper introduces the fundamental concepts of fault tolerant computing. Key topics covered are voting, fault detection, clock synchronization, Byzantine Agreement, diagnosis, and reliability analysis. Low level mechanisms such as Hamming codes or low level communications protocols are not covered. The paper is tutorial in nature and does not cover any topic in detail. The focus is on rationale and approach rather than detailed exposition

Information Leakage Attacks and Countermeasures

The scientific community has been consistently working on the pervasive problem of information leakage, uncovering numerous attack vectors, and proposing various countermeasures. Despite these efforts, leakage incidents remain prevalent, as the complexity of systems and protocols increases, and sophisticated modeling methods become more accessible to adversaries. This work studies how information leakages manifest in and impact interconnected systems and their users. We first focus on online communications and investigate leakages in the Transport Layer Security protocol (TLS). Using modern machine learning models, we show that an eavesdropping adversary can efficiently exploit meta-information (e.g., packet size) not protected by the TLS’ encryption to launch fingerprinting attacks at an unprecedented scale even under non-optimal conditions. We then turn our attention to ultrasonic communications, and discuss their security shortcomings and how adversaries could exploit them to compromise anonymity network users (even though they aim to offer a greater level of privacy compared to TLS). Following up on these, we delve into physical layer leakages that concern a wide array of (networked) systems such as servers, embedded nodes, Tor relays, and hardware cryptocurrency wallets. We revisit location-based side-channel attacks and develop an exploitation neural network. Our model demonstrates the capabilities of a modern adversary but also presents an inexpensive tool to be used by auditors for detecting such leakages early on during the development cycle. Subsequently, we investigate techniques that further minimize the impact of leakages found in production components. Our proposed system design distributes both the custody of secrets and the cryptographic operation execution across several components, thus making the exploitation of leaks difficult

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Architecture of a Microgrid and Optimal Energy Management System

With the growing population trends, the demand for electricity is accelerating rapidly. The policy planners and developers have great focus to utilize renewable energy resources (RERs) to encounter the scarcity of energy since they offer benefits to the environment and power systems. At present, the energy generation is evolving into a smart distribution system that assimilates several energy resources assuring to generate clean energy, to have reliable operational procedures, and to enhance the energy supervision and management arrangements. Therefore, the model of a distributed microgrid (DMG) with optimal energy management strategies based on multi-agent systems (MASs) technique has been focused in this chapter. Distributed energy resources (DER) have been considered for the generation of electrical power to fulfill the consumer’s load demands. Thus, a fully controlled architecture of a grid along with concept of MAS and its development platforms, implementation, and operational procedures have been discussed in detail. In addition, agent’s operations and their coordination within the MG arrangements have been focused by considering the supervision of the entire system autonomously. Moreover, optimal procedures of a microgrid (MG) energy supervision and power distribution system have also been presented considering the cost control and optimal operations of the entire MG at the distributed level