Acceleration Techniques for Sparse Recovery Based Plane-wave Decomposition of a Sound Field

Plane-wave decomposition by sparse recovery is a reliable and accurate technique for plane-wave decomposition which can be used for source localization, beamforming, etc. In this work, we introduce techniques to accelerate the plane-wave decomposition by sparse recovery. The method consists of two main algorithms which are spherical Fourier transformation (SFT) and sparse recovery. Comparing the two algorithms, the sparse recovery is the most computationally intensive. We implement the SFT on an FPGA and the sparse recovery on a multithreaded computing platform. Then the multithreaded computing platform could be fully utilized for the sparse recovery. On the other hand, implementing the SFT on an FPGA helps to flexibly integrate the microphones and improve the portability of the microphone array. For implementing the SFT on an FPGA, we develop a scalable FPGA design model that enables the quick design of the SFT architecture on FPGAs. The model considers the number of microphones, the number of SFT channels and the cost of the FPGA and provides the design of a resource optimized and cost-effective FPGA architecture as the output. Then we investigate the performance of the sparse recovery algorithm executed on various multithreaded computing platforms (i.e., chip-multiprocessor, multiprocessor, GPU, manycore). Finally, we investigate the influence of modifying the dictionary size on the computational performance and the accuracy of the sparse recovery algorithms. We introduce novel sparse-recovery techniques which use non-uniform dictionaries to improve the performance of the sparse recovery on a parallel architecture

Study of a low cost inertial platfom for a femto-satellite deployed by a mini-launcher

Durante este TFC, el estudiante trabaja de forma intensa en la modelización y validación para el espacio de una plataforma inercial así como de un estudio del impacto en la trayectoria deribado del error de la plataforma inercial. En una primera fase se define lo que es un femto-satélite y una mini-lanzadera. Se presenta la tecnología de bajo coste para el espacio y el paradigma 'space payload', es decir, realizar un diseño de ingeniería en función de la carga de pago y no en función de la industria. Se describe el programa de espacio WikiSat donde se define un femto-satélite en concreto que cumple con los requisitos del concurso N-Prize y de su mini-lanzadera. También se genera una lista de subsistemas que forman el binomio satélite-lanzadera. La parte importante de este TFC gira al rededor de la caracterización de la plataforma inercial que va a llevar el femto-satélite y que va a dirigir la trayectoria de la misma mini-lanzadera a fin de obtener sus actuaciones, asegurando que la fiabilidad de dicho componente se corresponde con los requerimientos de sistemas Single-Fault-Tolerant sin redundancia. Se define una librería para gestionar los datos inerciales de los acelerómetros, giróscopos y datos atmosféricos / eléctricos que nos permite corregir los errores que se producen en diferentes condiciones de trabajo. Por último se valida la plataforma inercial en cuanto a calificarla para el espacio (Radiación, vacío, cambios térmicos, etc.) apoyado con alguna simulación en SPENVIS y ensayo real. También se realiza un estudio de la trayectoria usada en el programa de espacio WikiSat, a fin de modelizar las condiciones en las que se va a encontrar dicha plataforma en el femto-satélite y la mini-lanzadera. Este estudio está basado en la presuposición de la alteración de la trayectoria debido a fallos de motor o errores introducidos en el control de navegación a fin de determinar una política de actuación de emergencia del sistema de autodestrucción

SYSTEM-ON-A-CHIP (SOC)-BASED HARDWARE ACCELERATION FOR HUMAN ACTION RECOGNITION WITH CORE COMPONENTS

Today, the implementation of machine vision algorithms on embedded platforms or in portable systems is growing rapidly due to the demand for machine vision in daily human life. Among the applications of machine vision, human action and activity recognition has become an active research area, and market demand for providing integrated smart security systems is growing rapidly. Among the available approaches, embedded vision is in the top tier; however, current embedded platforms may not be able to fully exploit the potential performance of machine vision algorithms, especially in terms of low power consumption. Complex algorithms can impose immense computation and communication demands, especially action recognition algorithms, which require various stages of preprocessing, processing and machine learning blocks that need to operate concurrently. The market demands embedded platforms that operate with a power consumption of only a few watts. Attempts have been mad to improve the performance of traditional embedded approaches by adding more powerful processors; this solution may solve the computation problem but increases the power consumption. System-on-a-chip eld-programmable gate arrays (SoC-FPGAs) have emerged as a major architecture approach for improving power eciency while increasing computational performance. In a SoC-FPGA, an embedded processor and an FPGA serving as an accelerator are fabricated in the same die to simultaneously improve power consumption and performance. Still, current SoC-FPGA-based vision implementations either shy away from supporting complex and adaptive vision algorithms or operate at very limited resolutions due to the immense communication and computation demands. The aim of this research is to develop a SoC-based hardware acceleration workflow for the realization of advanced vision algorithms. Hardware acceleration can improve performance for highly complex mathematical calculations or repeated functions. The performance of a SoC system can thus be improved by using hardware acceleration method to accelerate the element that incurs the highest performance overhead. The outcome of this research could be used for the implementation of various vision algorithms, such as face recognition, object detection or object tracking, on embedded platforms. The contributions of SoC-based hardware acceleration for hardware-software codesign platforms include the following: (1) development of frameworks for complex human action recognition in both 2D and 3D; (2) realization of a framework with four main implemented IPs, namely, foreground and background subtraction (foreground probability), human detection, 2D/3D point-of-interest detection and feature extraction, and OS-ELM as a machine learning algorithm for action identication; (3) use of an FPGA-based hardware acceleration method to resolve system bottlenecks and improve system performance; and (4) measurement and analysis of system specications, such as the acceleration factor, power consumption, and resource utilization. Experimental results show that the proposed SoC-based hardware acceleration approach provides better performance in terms of the acceleration factor, resource utilization and power consumption among all recent works. In addition, a comparison of the accuracy of the framework that runs on the proposed embedded platform (SoCFPGA) with the accuracy of other PC-based frameworks shows that the proposed approach outperforms most other approaches

SEIS: Insight's Seismic Experiment for Internal Structure of Mars.

By the end of 2018, 42 years after the landing of the two Viking seismometers on Mars, InSight will deploy onto Mars' surface the SEIS (Seismic Experiment for Internal Structure) instrument; a six-axes seismometer equipped with both a long-period three-axes Very Broad Band (VBB) instrument and a three-axes short-period (SP) instrument. These six sensors will cover a broad range of the seismic bandwidth, from 0.01 Hz to 50 Hz, with possible extension to longer periods. Data will be transmitted in the form of three continuous VBB components at 2 sample per second (sps), an estimation of the short period energy content from the SP at 1 sps and a continuous compound VBB/SP vertical axis at 10 sps. The continuous streams will be augmented by requested event data with sample rates from 20 to 100 sps. SEIS will improve upon the existing resolution of Viking's Mars seismic monitoring by a factor of ∼ 2500 at 1 Hz and ∼ 200 000 at 0.1 Hz. An additional major improvement is that, contrary to Viking, the seismometers will be deployed via a robotic arm directly onto Mars' surface and will be protected against temperature and wind by highly efficient thermal and wind shielding. Based on existing knowledge of Mars, it is reasonable to infer a moment magnitude detection threshold of M w ∼ 3 at 40 ∘ epicentral distance and a potential to detect several tens of quakes and about five impacts per year. In this paper, we first describe the science goals of the experiment and the rationale used to define its requirements. We then provide a detailed description of the hardware, from the sensors to the deployment system and associated performance, including transfer functions of the seismic sensors and temperature sensors. We conclude by describing the experiment ground segment, including data processing services, outreach and education networks and provide a description of the format to be used for future data distribution.Electronic supplementary materialThe online version of this article (10.1007/s11214-018-0574-6) contains supplementary material, which is available to authorized users

FLEXIBLE LOW-COST HW/SW ARCHITECTURES FOR TEST, CALIBRATION AND CONDITIONING OF MEMS SENSOR SYSTEMS

During the last years smart sensors based on Micro-Electro-Mechanical systems (MEMS) are widely spreading over various fields as automotive, biomedical, optical and consumer, and nowadays they represent the outstanding state of the art. The reasons of their diffusion is related to the capability to measure physical and chemical information using miniaturized components. The developing of this kind of architectures, due to the heterogeneities of their components, requires a very complex design flow, due to the utilization of both mechanical parts typical of the MEMS sensor and electronic components for the interfacing and the conditioning. In these kind of systems testing activities gain a considerable importance, and they concern various phases of the life-cycle of a MEMS based system. Indeed, since the design phase of the sensor, the validation of the design by the extraction of characteristic parameters is important, because they are necessary to design the sensor interface circuit. Moreover, this kind of architecture requires techniques for the calibration and the evaluation of the whole system in addition to the traditional methods for the testing of the control circuitry. The first part of this research work addresses the testing optimization by the developing of different hardware/software architecture for the different testing stages of the developing flow of a MEMS based system. A flexible and low-cost platform for the characterization and the prototyping of MEMS sensors has been developed in order to provide an environment that allows also to support the design of the sensor interface. To reduce the reengineering time requested during the verification testing a universal client-server architecture has been designed to provide a unique framework to test different kind of devices, using different development environment and programming languages. Because the use of ATE during the engineering phase of the calibration algorithm is expensive in terms of ATE’s occupation time, since it requires the interruption of the production process, a flexible and easily adaptable low-cost hardware/software architecture for the calibration and the evaluation of the performance has been developed in order to allow the developing of the calibration algorithm in a user-friendly environment that permits also to realize a small and medium volume production. The second part of the research work deals with a topic that is becoming ever more important in the field of applications for MEMS sensors, and concerns the capability to combine information extracted from different typologies of sensors (typically accelerometers, gyroscopes and magnetometers) to obtain more complex information. In this context two different algorithm for the sensor fusion has been analyzed and developed: the first one is a fully software algorithm that has been used as a means to estimate how much the errors in MEMS sensor data affect the estimation of the parameter computed using a sensor fusion algorithm; the second one, instead, is a sensor fusion algorithm based on a simplified Kalman filter. Starting from this algorithm, a bit-true model in Mathworks Simulink(TM) has been created as a system study for the implementation of the algorithm on chip

Study of a low cost inertial platfom for a femto-satellite deployed by a mini-launcher

Durante este TFC, el estudiante trabaja de forma intensa en la modelización y validación para el espacio de una plataforma inercial así como de un estudio del impacto en la trayectoria deribado del error de la plataforma inercial. En una primera fase se define lo que es un femto-satélite y una mini-lanzadera. Se presenta la tecnología de bajo coste para el espacio y el paradigma 'space payload', es decir, realizar un diseño de ingeniería en función de la carga de pago y no en función de la industria. Se describe el programa de espacio WikiSat donde se define un femto-satélite en concreto que cumple con los requisitos del concurso N-Prize y de su mini-lanzadera. También se genera una lista de subsistemas que forman el binomio satélite-lanzadera. La parte importante de este TFC gira al rededor de la caracterización de la plataforma inercial que va a llevar el femto-satélite y que va a dirigir la trayectoria de la misma mini-lanzadera a fin de obtener sus actuaciones, asegurando que la fiabilidad de dicho componente se corresponde con los requerimientos de sistemas Single-Fault-Tolerant sin redundancia. Se define una librería para gestionar los datos inerciales de los acelerómetros, giróscopos y datos atmosféricos / eléctricos que nos permite corregir los errores que se producen en diferentes condiciones de trabajo. Por último se valida la plataforma inercial en cuanto a calificarla para el espacio (Radiación, vacío, cambios térmicos, etc.) apoyado con alguna simulación en SPENVIS y ensayo real. También se realiza un estudio de la trayectoria usada en el programa de espacio WikiSat, a fin de modelizar las condiciones en las que se va a encontrar dicha plataforma en el femto-satélite y la mini-lanzadera. Este estudio está basado en la presuposición de la alteración de la trayectoria debido a fallos de motor o errores introducidos en el control de navegación a fin de determinar una política de actuación de emergencia del sistema de autodestrucción

Design and implementation of a modular controller for robotic machines

This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design incorporates novel communication, hardware, and software architectures. This was motivated by current industrial needs for distributed control systems due to growing demand for less complexity, more processing power, flexibility, and greater fault tolerance. To this end, three main contributions were made. Most distributed control architectures depend on multi-tier heterogeneous communication networks requiring linking devices and/or complex middleware. In this study, first, a communication architecture was proposed and implemented with a homogenous network employing the ubiquitous Ethernet for both real-time and non real-time communication. This was achieved by a producer-consumer coordination model for real-time data communication over a segmented network, and a client-server model for point-to-point transactions. The protocols deployed use a Time-Triggered (TT) approach to schedule real-time tasks on the network. Unlike other TT approaches, the scheduling mechanism does not need to be configured explicitly when controller nodes are added or removed. An implicit clock synchronization technique was also developed to complement the architecture. Second, a reconfigurable mechanism based on an auto-configuration protocol was developed. Modules on the network use this protocol to automatically detect themselves, establish communication, and negotiate for a desired configuration. Third, the research demonstrated hardware/software co-design as a contribution to the growing discipline of mechatronics. The IMC consists of a motion controller board designed and prototyped in-house, and a Java microcontroller. An IMC is mapped to each machine/robot axis, and an additional IMC can be configured to serve as a real-time coordinator. The entire architecture was implemented in Java, thus reinforcing uniformity, simplicity, modularity, and openness. Evaluation results showed the potential of the flexible controller to meet medium to high performance machining requirements

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

Actualmente, las tecnologías CMOS submicrónicas son básicas para el desarrollo de los modernos sistemas basados en computadores, cuyo uso simplifica enormemente nuestra vida diaria en una gran variedad de entornos, como el gobierno, comercio y banca electrónicos, y el transporte terrestre y aeroespacial. La continua reducción del tamaño de los transistores ha permitido reducir su consumo y aumentar su frecuencia de funcionamiento, obteniendo por ello un mayor rendimiento global. Sin embargo, estas mismas características que mejoran el rendimiento del sistema, afectan negativamente a su confiabilidad. El uso de transistores de tamaño reducido, bajo consumo y alta velocidad, está incrementando la diversidad de fallos que pueden afectar al sistema y su probabilidad de aparición. Por lo tanto, existe un gran interés en desarrollar nuevas y eficientes técnicas para evaluar la confiabilidad, en presencia de fallos, de sistemas fabricados mediante tecnologías submicrónicas. Este problema puede abordarse por medio de la introducción deliberada de fallos en el sistema, técnica conocida como inyección de fallos. En este contexto, la inyección basada en modelos resulta muy interesante, ya que permite evaluar la confiabilidad del sistema en las primeras etapas de su ciclo de desarrollo, reduciendo por tanto el coste asociado a la corrección de errores. Sin embargo, el tiempo de simulación de modelos grandes y complejos imposibilita su aplicación en un gran número de ocasiones. Esta tesis se centra en el uso de dispositivos lógicos programables de tipo FPGA (Field-Programmable Gate Arrays) para acelerar los experimentos de inyección de fallos basados en simulación por medio de su implementación en hardware reconfigurable. Para ello, se extiende la investigación existente en inyección de fallos basada en FPGA en dos direcciones distintas: i) se realiza un estudio de las tecnologías submicrónicas existentes para obtener un conjunto representativo de modelos de fallos transitoriosAndrés Martínez, DD. (2007). Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1943Palanci