MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

UMTV: a Single Chip TV Receiver for PDAs, PCs and Cell Phones

A zero-external-component TV receiver for portable platforms is realized in a mainstream 8GHz-f/sub t/ BiCMOS process. Die size is 5/spl times/5mm/sup 2/ and power dissipation is 50mA at 3V. The receiver includes a single tunable LNA (3mA) with less than 5dB NF from 40 to 900MHz. The programmable IF filters cover all analog and digital standards

메모리 인터페이스를 위한 멀티 레벨 단일 종단 송신기 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2020. 8. 김수환.본 연구에서 메모리 인터페이스를 위한 멀티 레벨 송신기가 제시되었다. 프로세서와 메모리 간의 성능 차이가 매년 계속 증가함에 따라, 메모리는 전체 시스템의 병목점이 되고있다. 우리는 메모리 대역폭을 늘리기 위해 PAM-4 단일 종단 송신기를 제안하였고, 멀티 랭크 메모리를 위한 duobinary 단일 종단 송신기를 제안하였다. 제안된 PAM-4 송신기의 드라이버는 높은 선형성과 임피던스 정합을 동시에 만족한다. 또한 저항이나 인덕터를 사용하지 않아 작은 면적을 차지한다. 제안된 ZQ 캘리브레이션은 세개의 교정 점을 가지고 있어 송신기가 정확한 임피던스와 선형적인 출력을 갖게 한다. 프로토 타입은 65nm CMOS 공정으로 제작되었고 송신기는 0.0333mm2의 면적을 차지한다. 측정된 28Gb/s에서의 eye는 18.3ps의 길이와 42.4mV의 높이를 갖고, 에너지 효율은 0.64pJ/bit이다. ZQ 캘리브레이션과 함께 측정된 RLM은 0.993이다. 메모리의 용량을 늘리기 위해 하나의 패키지에 여러 개의 DRAM 다이를 수직으로 쌓는 패키징은 메모리의 중앙 패드 구조와 결합되어 짧은 반사를 야기하는 스텁을 만든다. 우리는 이 문제를 완화하기위해 반사 기반 duobinary 송신기를 제안했다. 이 송신기는 반사를 이용하여 duobinary signaling을 한다. 2탭 반대 강조 기술과 슬루 레이트 조절 기술이 신호 완결성을 높이기 위해 사용되었다. NRZ eye가 없는 10Gb/s에서 측정된 duobinary eye는 63.6ps 길이와 70.8mV의 높이를 갖는다. 측정된 에너지 효율은 1.38pJ/bit이다.Multi-level transmitters for memory interfaces have been presented. The performance gap between processor and memory has been increased by 50% every year, making memory to be a bottle neck of the overall system. To increase memory bandwidth, we have proposed a PAM-4 single-ended transmitter. To compensate for the side effect of the multi-rank memory, we have proposed a reflection-based duobinary transmitter. The proposed PAM-4 transmitter has the driver, which simultaneously satisfies impedance matching and high linearity. The driver occupies a small area due to a resistorless and inductorless structure. The proposed ZQ calibration for PAM-4 has three calibration points, which allow the transmitter to have accurate impedance and linear output. The ZQ calibration considers impedance variation of both the driver and the receiver. A prototype has been fabricated in 65nm CMOS process, and the transmitter occupies 0.0333mm2. The measured eye has a width of 18.3ps and a height of 42.4mV at 28Gb/s, and the measured energy efficiency is 0.64pJ/b. The measured RLM with the 3-point ZQ calibration is 0.993. To increase memory density, the stacked die packaging with multiple DRAM die stacked vertically in one package is widely used. However, combined with the center-pad structure, the structure creates stubs that cause short reflections. We have proposed the reflection-based duobinary transmitter to mitigate this problem. The proposed transmitter uses reflection for duobinary signaling. The 2-tap opposite FFE and the slew-rate control are used to increase signal integrity. The measured duobinary eye at 10Gb/s has a width of 63.6ps and a height of 70.8mV while there is no NRZ eye opening. The measured energy efficiency is 1.38pJ/bit.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 8 CHAPTER 2 MUTI-LEVEL SIGNALING 9 2.1 PAM-4 SIGNALING 9 2.2 DESIGN CONSIDERATIONS FOR PAM-4 TRANSMITTER 16 2.2.1 LEVEL SEPARATION MISMATCH RATIO (RLM) 17 2.2.2 IMPEDANCE MATCHING 19 2.2.3 PRIOR ARTS 21 2.3 DUOBINARY SIGNALING 24 CHAPTER 3 HIGH-LINEARITY AND IMPEDANCE-MATCHED PAM-4 TRANSMITTER 30 3.1 OVERALL ARCHITECTURE 31 3.2 SINGLE-ENDED IMPEDANCE-MATCHED PAM-4 DRIVER 33 3.3 3-POINT ZQ CALIBRATION FOR PAM-4 47 CHAPTER 4 REFLECTION-BASED DUOBINARY TRANSMITTER 57 4.1 BIDIRECTIONAL DUAL-RANK MEMORY SYSTEM 58 4.2 CONCEPT OF REFLECTION-BASED DUOBINARY SIGNALING 66 4.3 REFLECTION-BASED DUOBINARY TRANSMITTER 70 4.3.1 OVERALL ARCHITECTURE 70 4.3.2 EQUALIZATION FOR REFLECTION-BASED DUOBINARY SIGNALING 72 4.3.3 2D BINARY-SEGMENTED DRIVER 75 CHAPTER 5 EXPERIMENTAL RESULTS 77 5.1 HIGH-LINEARITY AND IMPEDANCE-MATCHED PAM-4 TRANSMITTER 77 5.2 REFLECTION-BASED DUOBINARY TRANSMITTER 84 CHAPTER 6 92 CONCLUSION 92 BIBLIOGRAPHY 94Docto

EMI Susceptibility Issue in Analog Front-End for Sensor Applications

The susceptibility to electromagnetic interferences of the analog circuits used in the sensor readout front-end is discussed. Analog circuits still play indeed a crucial role in sensor signal acquisition due to the analog nature of sensory signals. The effect of electromagnetic interferences has been simulated and measured in many commercial and integrated analog circuits; the main cause of the electromagnetic susceptibility is investigated and the guidelines to design high EMI immunity circuits are provided

AlInP photodiode x-ray detectors

Four Al0.52In0.48P p+-i-n+ mesa photodiodes with 6 μm thick i layers and two different diameters (217 μm  ±  15 μm and 409 μm  ±  28 μm) were studied at room temperature (24 °C). Electrical characterisation measurements are reported along with measurements showing the performance of the devices as x-ray detectors. The devices exhibited leakage currents  <3 pA (corresponding to leakage current densities  <2 nA cm−2) at 100 V reverse bias (electric field strength of 167 kV cm−1). The photodiodes were coupled to a custom-made low-noise charge-sensitive preamplifier, the noise characteristics of the resultant spectrometers were investigated as functions of shaping times. The best energy resolutions (full width at half maximum of the 5.9 keV photopeak from an 55Fe radioisotope x-ray source) achieved with the 217 μm  ±  15 μm and 409 μm  ±  28 μm diameter photodiodes were 0.89 keV and 1.05 keV, respectively. The dielectric dissipation factor of Al0.52In0.48P was estimated to be (2.2  ±  1.1)  ×  10−3 at room temperature

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

ISM-Band Energy Harvesting Wireless Sensor Node

In recent years, the interest in remote wireless sensor networks has grown significantly, particularly with the rapid advancements in Internet of Things (IoT) technology. These networks find diverse applications, from inventory tracking to environmental monitoring. In remote areas where grid access is unavailable, wireless sensors are commonly powered by batteries, which imposes a constraint on their lifespan. However, with the emergence of wireless energy harvesting technologies, there is a transformative potential in addressing the power challenges faced by these sensors. By harnessing energy from the surrounding environment, such as solar, thermal, vibrational, or RF sources, these sensors can potentially operate autonomously for extended periods. This innovation not only enhances the sustainability of wireless sensor networks but also paves the way for a more energy-efficient and environmentally conscious approach to data collection and monitoring in various applications. This work explores the development of an RF-powered wireless sensor node in 22nm FDSOI technology working in the ISM band for energy harvesting and wireless data transmission. The sensor node encompasses power-efficient circuits, including an RF energy harvesting module equipped with a multi-stage RF Dickson rectifier, a robust power management unit, a DLL and XOR-based frequency synthesizer for RF carrier generation, and a class E power amplifier. To ensure the reliability of the WSN, a dedicated wireless RF source powers up the WSN. Additionally, the RF signal from this dedicated source serves as the reference frequency input signal for synthesizing the RF carrier for wireless data transmission, eliminating the need for an on-chip local oscillator. This approach achieves high integration and proves to be a cost-effective implementation of efficient wireless sensor nodes. The receiver and energy harvester operate at 915 MHz Frequency, while the transmitter functions at 2.45 GHz, employing On-Off Keying (OOK) for data modulation. The WSN utilizes an efficient RF rectifier design featuring a remarkable power conversion efficiency, reaching 55% at an input power of -14 dBm. Thus, the sensor node can operate effectively even with an extremely low RF input power of -25 dBm. The work demonstrates the integration of the wireless sensor node with an ultra-low-power temperature sensor, designed using 65 nm CMOS technology. This temperature sensor features an ultra-low power consumption of 60 nW and a Figure of Merit (FOM) of 0.022 [nJ.K-2]. The WSN demonstrated 55% power efficiency at a TX output power of -3.8 dBm utilizing a class E power amplifier

Development of a Sensor Readout Integrated Circuit Towards a Contact Lens for Wireless Intraocular Pressure Monitoring

This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA

Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process

The rapid shrinking of feature sizes in CMOS processes has enabled high density integration of multi-core systems. However, the corresponding increase in component and local power densities induces thermal stress that can severely affect the reliability of the integrated circuits. To improve the power and thermal management for multi-core systems, an array of temperature sensors is now used to locally monitor the die temperature and provide feedback to the controller for efficient load management and/or load balancing. These temperature sensors must be very small (minimum area overhead) and low power, must have low supply sensitivity, and must provide accurate temperature measurements over a limited operating range. This thesis provides fundamental analysis of a CMOS Widlar reference generator and the synthesis of a P-Type reverse Widlar temperature sensor. This is followed by the introduction of a 4-transistor multiple threshold voltage (multi-VT) based temperature sensor. Power supply sensitivity analysis and noise analysis are provided for both the 5-transistors reverse Widlar structure and the 4-transistors multi-VT structure. A full design example of a cascoded multi-VT temperature sensor based upon the low-voltage 4-transistor temperature sensor core is also presented. The cascoded structure includes self-bias generators for biasing of the cascode transistors. The proposed cascode multi-VT temperature sensor based upon the 4-transistor temperature sensor core is implemented in a digital 65nm process with a 1.2V supply voltage. The circuit expresses the threshold voltage directly at the output, does not require a start-up circuit, and provides temperature measurement over an extended operating range. In this thesis, focus is on how the sensor performs over the -20yC to 100yC temperature range. This sensor can achieve high temperature linearity over this operating range. In a design example of the cascoded 4-transistor multi-VT sensor implemented in a 65nm process, simulation results were obtained that show a maximum nonlinearity over all process corners of 0.546yC over a 120yC operating range. The supply sensitivity is small with a total variation of 0.44yC due to a y10% variation in the supply voltage. The combined temperature nonlinearity and temperature error due to supply variations is less than 1yC. A detailed discussion of the operation of the cascode self-biasing circuits relating to stability, start-up circuits, and equilibrium points is presented. By adapting the contraction mapping principle to the multi-loop self-biased multi-VT temperature sensor, it is shown that the proposed circuit has a single stable equilibrium point and thus does not require a startup circuit