Mechanical and electrical characterisation of anisotropic conductive adhesive particles

This thesis presents research into the mechanical and electrical characterisation of Anisotropic Conductive Adhesive (ACA) particles and their behaviour within typical joints. A new technique has been developed for study of individual ACA particle mechanical and electrical performance when undergoing deformation. A study of the effects of planarity variations on individual electrical joints in real ACA assemblies is presented firstly, followed by the research on the mechanical deformation and electrical tests of individual ACA particles undergoing deformation. In the co-planarity research, experiments introducing deliberate rotation between a chip and substrate were designed and carried out to simulate planarity variations in ACA assemblies. There are two outputs from this part of the research. One is the planarity variation effects on individual electrical joints in ACA assemblies, and the other is the effect of bond thickness on the resistance of a real joint. [Continues.

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

Technical Design Report for the: PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined.Comment: 189 pages, 225 figures, 41 table

Voyager spacecraft system, phase IA, TASK B - Preliminary design. Spacecraft functional design, volume A, book 2

Functional descriptions of subsystems for 1971 Voyager flight spacecraf

Komponentin liittäminen venyvälle alustalle puettavan elektroniikan sovelluksissa

Wearable electronics is a new growing field of technology. Many companies have introduced wearable electronics applications, mostly related to the fields of fitness or healthcare. The wearable device should be able to be worn unobtrusively and safely. In order to guarantee those the stretchable electronics may be a more suitable option than conventional rigid electronics or even flexible electronics. One way to implement a stretchable electronics circuit is by miniaturizing functional modules to small rigid functional islands. The islands can be mounted on the stretchable substrate by an adhesive and connected to each other with stretchable interconnects. In this thesis, the aim is to manufacture and evaluate adhesive joints of a different kind between the stretchable substrate and the rigid component. First in this thesis, the theoretical background of the stretchable materials, of the adhesives and of the manufacturing processes is studied. For testing the adhesive joints, the test samples with screen-printed interconnects are manufactured. Then the components are mounted on the substrates by adhesives and the initial electrical properties of the samples are measured. After that the uniaxial cyclic stretch test is implemented where the resistances of the samples are measured continuously using 4-point measurements. The one-time elasticity test is implemented only with the best combination of the adhesive and the substrate. In addition in this thesis, a custom-made test setup is designed and executed which aim is to stretch the sample for the same amount in every direction at the same time. The functionality of the setup is evaluated by comparing it with the other test setup. There were two main quality issues related to the screen-printing process. Firstly, the ink cracked on one substrate and secondly, the impurities weakened the quality of the printed traces. Although the measured sheet resistance values of the ink were higher than in the datasheet of the ink was reported they were still sufficient for this thesis. Only the samples that had all the four measurement channels with an initial resistance lower than 110 Ω were accepted to the strain tests. In addition to the adhesive joint, the measurement included also the resistance of the component and of the small parts of the printed wires. During the strain test, the samples were stretched 10 % for 500 times. The variation between the samples was high, even with the samples with the same combination of the adhesive and the substrate. However, one adhesive performed better than the others. Thus, it was used also in the comparison between the test setups. With the custom-made test setup, the samples lost the connection with a lower uniaxial measured extension, so the setup functioned as expected

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

NASA Tech Briefs, August 2000

Topics include: Simulation/Virtual Reality; Test and Measurement; Computer-Aided Design and Engineering; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences; Medical Design