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Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs
For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs
Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization
This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55ยฐC to 125ยฐC, 15ยฐC/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region
์ฐจ์ธ๋ ๋ฐ๋์ฒด ๋ฐฐ์ ์ ์ํ ์ฝ๋ฐํธ ํฉ๊ธ ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง ์ฌ๋ฃ ์ค๊ณ ๋ฐ ์ ๊ธฐ์ ์ ๋ขฐ์ฑ์ ๋ํ ์ฐ๊ตฌ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ฌ๋ฃ๊ณตํ๋ถ, 2022.2. ์ฃผ์์ฐฝ.Recently, the resistance-capacitance (RC) delay of the Cu interconnects in metal 1 (M1) level has been increased rapidly due to the reduction of the interconnect linewidth along with the transistor scaling down, and the interconnect reliability becomes a severe issue again. In order to overcome interconnect performance problems and move forward to the next-generation interconnects system, study on low resistivity (ฯo) and low electron mean free path (ฮป) metals was conducted. Generally, metals such as Cobalt (Co), Ruthenium (Ru), and Molybdenum (Mo) are mentioned as candidates for next-generation interconnect materials, and since they have a low ฯo ร ฮป value, it is expected that the influence of interface scatterings and surface scattering can be minimized. However, harsh operating environments such as high electric fields, critical Joule heating, and reduction of the pitch size are severely deteriorating the performance of electronic devices as well as device reliability. For example, since time dependent dielectric breakdown (TDDB) problems for next-generation interconnect system have been reported recently, it is necessary to study alternative barrier materials and processes to improve the interconnect reliability. Specifically, extrinsic dielectric breakdown due to penetration of Co metal ions in high electric fields has been reported as a reliability problem to be solved in Co interconnect systems. Therefore, there is a need for new material system design and research on a robust diffusion barrier that prevents metal ions from penetrating into the dielectric, thereby improving the reliability of Co interconnects. Moreover, in order to lower the resistance of the interconnect, it is necessary to develop an ultra-thin barrier. This is because even a barrier with good reliability characteristics will degrade chip performance if it takes up a lot of volume in the interconnect. The recommended thickness for a single diffusion barrier layer is currently reported to be less than 2.5 nm. As a result, it is essential to develop materials that comprehensively consider performance and reliability.
In this study, we designed a Co alloy self-forming barrier (SFB) material that can make sure of low resistance and high reliability for Co interconnects, which is attracting attention as a next-generation interconnect system. The self-forming barrier methodology induces diffusion of an alloy dopant at the interface between the metal and the dielectric during the annealing process. And the diffused dopant reacts with the dielectric to form an ultra-thin diffusion barrier. Through this methodology, it is possible to improve reliability by preventing the movement of metal ions. First of all, material design rules were established to screen the appropriate alloy dopants and all CMOS-compatible metals were investigated. Dopant resistivity, intermetallic compound formation, solubility in Co, activity coefficient in Co, and oxidation tendency is considered as the criteria for the dopant to escape from the Co matrix and react at the Co/SiO2 interface. In addition, thermodynamic calculations were performed to predict which phases would be formed after the annealing process. Based on thermodynamic calculations, 5 dopant metals were selected, prioritized for self-forming behavior. And the self-forming material was finally selected through thin film and device analysis. We confirmed that Cr, Zn, and Mn out-diffused to the surface of the thin film structure using X-ray photoelectron spectroscopy (XPS) depth profile and investigated the chemical state of out-diffused dopants through the analysis of a binding energy. Cr shows the most ideal self-forming behavior with the SiO2 dielectric and reacted with oxygen to form a Cr2O3 barrier. In metal-insulator-semiconductor (MIS) structure, out-diffused Cr reacts with SiO2 at the interface and forms a self-formed single layer. It was confirmed that the thickness of the diffusion barrier layer is about 1.2 nm, which is an ultra-thin layer capable of minimizing the total effective resistance. Through voltage-ramping dielectric breakdown (VRDB) tests, Co-Cr alloy showed highest breakdown voltage (VBD) up to 200 % than pure Co. The effect of Cr doping concentration and heat treatment condition applicable to the interconnect process was confirmed. When Cr was doped less than 1 at%, the robust electrical reliability was exhibited. Also, it was found that a Cr2O3 interfacial layer was formed when annealing process was performed at 250 ยฐC or higher for 30 minutes or longer. In other words, Co-Cr alloy is well suited for the interconnect process because current interconnect process temperature is below 400 ยฐC. And when the film thickness was lowered from 150 nm to 20 nm, excellent VBD values were confirmed even at high Cr doping concentration (~7.5 at%). It seems that the amount of Cr present at the Co/SiO2 interface plays a very important role in improving the Cr oxide SFB quality. Physical modeling is necessary to understand the amount of Cr at the interface according to the interconnect volumes and the reliability of the Cr oxide self-forming barrier. TDDB lifetime test also performed and Co-Cr alloy interconnect shows a highly reliable diffusion barrier property of self-formed interfacial layer. The DFT analysis also confirmed that Cr2O3 is a very promising barrier material because it showed a higher energy barrier value than the TiN diffusion barrier currently being studied.
A Co-based self-forming barrier was designed through thermodynamic calculations that take performance and reliability into account in interconnect material system. A Co interconnect system with an ultra-thin Cr2O3 diffusion barrier with excellent reliability is proposed. Through this design, it is expected that high-performance interconnects based on robust reliability in the advanced interconnect can be implemented in the near future.์ต๊ทผ ๋ฐ๋์ฒด ์์ ์ค์ผ์ผ๋ง์ ๋ฐ๋ฅธ ๋ฐฐ์ ์ ํญ ๊ฐ์๋ก M0, M1์์ญ์์์ metal ๋น์ ํญ์ด ๊ธ๊ฒฉํ ์ฆ๊ฐํ์ฌ ๋ฐฐ์ ์์์ RC delay๊ฐ ๋ค์ ํ๋ฒ ํฌ๊ฒ ๋ฌธ์ ๊ฐ ๋๊ณ ์๋ค. ์ด๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด์ ์ฐจ์ธ๋ ๋ฐฐ์ ์์คํ
์์๋ ๋ฎ์ ๋น์ ํญ๊ณผ electron mean free path (EMFP)์ ๊ฐ์ง๋ ๋ฌผ์ง ์ฐ๊ตฌ๊ฐ ์งํ๋์๋ค. ๋ํ์ ์ผ๋ก Co, Ru, Mo์ ๊ฐ์ ๊ธ์๋ค์ด ์ฐจ์ธ๋ ๋ฐฐ์ ์ฌ๋ฃ ํ๋ณด๋ก ์ธ๊ธ๋๊ณ ์์ผ๋ฉฐ ๋ฎ์ ฯ0 ร ฮป ๊ฐ์ ๊ฐ๊ธฐ ๋๋ฌธ์ interface (surface) scattering๊ณผ grain boundary scattering ์ํฅ์ ์ต์ํํ ์ ์์ ๊ฒ์ผ๋ก ๋ณด๊ณ ์๋ค. ํ์ง๋ง ๊ฐํนํ electrical field์ ๋์ Joule heating์ด ๋ฐ์ํ๋ ๋์ ํ๊ฒฝ์ผ๋ก ์ธํด performance๋ฟ๋ง ์๋๋ผ ์์ ์ ๋ขฐ์ฑ์ด ๋ ์ด์
ํ ์ํฉ์ ๋์ฌ์๋ค. ์๋ฅผ ๋ค์ด ์ฐจ์ธ๋ ๊ธ์์ ๋ํ time dependent dielectric breakdown (TDDB) ์ ๋ขฐ์ฑ ๋ฌธ์ ๊ฐ ๋ณด๊ณ ๋๊ณ ์๊ธฐ ๋๋ฌธ์ ์ด๋ฅผ ๋ณด์ํ ํ์ฐ๋ฐฉ์ง๋ง ๋ฌผ์ง ๋ฐ ๊ณต์ ์ฐ๊ตฌ๊ฐ ํ์ํ๋ค. ํนํ ๋์ ์ ๊ธฐ์ฅ์์ Co ion์ด ์ ์ ์ฒด๋ก ์นจํฌํ์ฌ extrinsic dielectric breakdown ์ ๋ขฐ์ฑ ๋ฌธ์ ๊ฐ ์ต๊ทผ ๋ณด๊ณ ๋๊ณ ์๋ค. ๋ฐ๋ผ์ ๊ธ์ ์ด์จ์ด ์ ์ ์ฒด ๋ด๋ถ๋ก ์นจํฌํ๋ ๊ฒ์ ๋ฐฉ์งํ์ฌ, Co ๋ฐฐ์ ์ ์ ๋ขฐ์ฑ์ ํฅ์์ํฌ ์ ๊ฒฌ๊ณ ํ ํ์ฐ๋ฐฉ์ง๋ง ๊ฐ๋ฐ ๋ฐ ์๋ก์ด ๋ฐฐ์ ์์คํ
์ค๊ณ๊ฐ ํ์ํ ์์ ์ด๋ค. ๋ํ, ๋ฐฐ์ ์ ํญ์ ๋ฎ์ถ๊ธฐ ์ํด์๋ ๋งค์ฐ ์์ ํ์ฐ๋ฐฉ์ง๋ง ๊ฐ๋ฐ์ด ํ์ํ๋ค. ์ ๋ขฐ์ฑ์ด ์ข์ ํ์ฐ๋ฐฉ์ง๋ง์ด๋ผ๋ ๋ฐฐ์ ์์ ๋ง์ ์์ญ์ ์ฐจ์งํ ๊ฒฝ์ฐ ์ ์ฒด ์ฑ๋ฅ์ด ์ ํ๋๊ธฐ ๋๋ฌธ์ด๋ค. Cu ํ์ฐ๋ฐฉ์ง๋ง์ผ๋ก ์ฌ์ฉ๋๊ณ ์๋ TaN ์ธต์ 2.5 nm ๋ณด๋ค ์์ ๊ฒฝ์ฐ ์ ๋ขฐ์ฑ์ด ๊ธ๊ฒฉํ ๋๋น ์ง๋ฏ๋ก 2.5 nm๋ณด๋ค ์์ ๋๊ป์ ๊ฒฌ๊ณ ํ ํ์ฐ๋ฐฉ์ง๋ง ๊ฐ๋ฐ์ด ํ์ํ๋ค.
๋ณธ ์ฐ๊ตฌ๋ ์ฐจ์ธ๋ ๋ฐ๋์ฒด ๋ฐฐ์ ๋ฌผ์ง๋ก ์ฃผ๋ชฉ๋ฐ๊ณ ์๋ Co ๊ธ์์ ๋ํ์ฌ ์ ์ ํญยท๊ณ ์ ๋ขฐ์ฑ์ ํ๋ณดํ ์ ์๋ Co alloy ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง (Co alloy self-forming barrier, SFB) ์์ฌ ๋์์ธํ์๋ค. ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง ๋ฐฉ๋ฒ๋ก ์ ์ด์ฒ๋ฆฌ ๊ณผ์ ์์ ๊ธ์๊ณผ ์ ์ ์ฒด ๊ณ๋ฉด์์ ๋ํํธ๊ฐ ํ์ฐํ๊ฒ ๋๋ค. ๊ทธ๋ฆฌ๊ณ ํ์ฐ๋๋ ๋ํํธ๋ ์์ ํ์ฐ๋ฐฉ์ง๋ง์ ํ์ฑํ๋ ๋ฐฉ๋ฒ๋ก ์ด๋ค. ์ด ๋ฐฉ๋ฒ๋ก ์ ํตํด ๊ธ์ ์ด์จ์ ์ด๋์ ๋ฐฉ์งํ์ฌ Co ๋ฐฐ์ ์ ๋ขฐ์ฑ์ ํฅ์์ํฌ ์ ์์ ๊ฒ์ผ๋ก ์์ํ์๋ค. ์ฐ์ , Co ํฉ๊ธ์์์ ์ ์ ํ ๋ํํธ๋ฅผ ์ฐพ๊ธฐ ์ํด์ CMOS ๊ณต์ ์ ์ ์ฉ ๊ฐ๋ฅํ ๊ธ์๋ค์ ์ ๋ณํ์๋ค. ๋ํํธ ์ ํญ, ๊ธ์๊ฐ ํํฉ๋ฌผ ํ์ฑ ์ฌ๋ถ, Co๋ด ๊ณ ์ฉ๋, Co alloy์์์ ํ์ฑ๊ณ์, ์ฐํ๋, Co/SiO2 ๊ณ๋ฉด์์์ ์์ ์์ ์ด์ญํ์ ๊ณ์ฐ์ ํตํด์ ๋ฌผ์ง ์ ์ ๊ธฐ์ค์ผ๋ก ์ธ์ ๋ค. ์ด์ญํ์ ๊ณ์ฐ์ ๊ธฐ๋ฐ์ผ๋ก 9๊ฐ์ ๋ํํธ ๊ธ์์ด ์ ํ๋์์ผ๋ฉฐ, Co ํฉ๊ธ ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง ๊ธฐ์ค์ ๋ฐ๋ผ์ ์ฐ์ ์์๋ฅผ ์ง์ ํ์๋ค. ๊ทธ๋ฆฌ๊ณ ์ต์ข
์ ์ผ๋ก ๋ฐ๋ง๊ณผ ์์ ์ ๋ขฐ์ฑ ํ๊ฐ๋ฅผ ํตํด์ ๊ฐ์ฅ ์ ํฉํ ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง ๋ฌผ์ง์ ์ ์ ํ์๋ค. X-ray photoelectron spectroscopy (XPS) ๋ถ์์ ์ด์ฉํ์ฌ Cr, Zn, Mn์ด ๋ฐ๋ง ๊ตฌ์กฐ์ ํ๋ฉด์ผ๋ก ์ธ๋ถ ํ์ฐ ์ฌ๋ถ๋ฅผ ํ์ธํ๊ณ ๊ฒฐํฉ ์๋์ง ๋ถ์์ ํตํด ์ธ๋ถ๋ก ํ์ฐ๋ ๋ํํธ์ ํํ์ ์ํ๋ฅผ ์กฐ์ฌํ์๋ค. ๋ถ์ ๊ฒฐ๊ณผ Cr, Zn, Mn์ด ์ ์ ์ฒด ๊ณ๋ฉด์ผ๋ก ํ์ฐ๋์ด ์ฐ์์ ๋ฐ์ํ์ฌoxide/silicate ํ์ฐ ๋ฐฉ์ง๋ง (e.g. Cr2O3, Zn2SiO4, MnSiO3)์ ํ์ฑํ ๊ฒ์ ํ์ธํ์๋ค. ๊ทธ ์ค Cr์ SiO2 ์ ์ ์ฒด์ ํจ๊ป ๊ฐ์ฅ ์ด์์ ์ธ ์๊ธฐ ํ์ฑ ๊ฑฐ๋์ ๋ํ๋ด๋ฉฐ ์ฐ์์ ๋ฐ์ํ์ฌ Cr2O3 ์ธต์ ํ์ฑํ๋ ๊ฒ์ ํ์ธํ์๋ค. MIS (Metal-Insulator-Semiconductor) ๊ตฌ์กฐ์์๋ ์ธ๋ถ๋ก ํ์ฐ๋ Cr์ ๊ณ๋ฉด์์ SiO2์ ๋ฐ์ํ์ฌ Cr2O3 ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง์ด ํ์ฑ๋์๋ค. ํ์ฐ๋ฐฉ์ง์ธต์ ๋๊ป๋ ์ฝ 1.2nm๋ก ์ ์ฒด ์ ํจ์ ํญ์ ์ต์ํํ ์ ์๋ ์ถฉ๋ถํ ์์ ๋๊ป๋ฅผ ํ๋ณดํ์๋ค. VRDB (Voltage-Ramping Dielectric Breakdown) ํ
์คํธ๋ฅผ ํตํด Co-Cr ํฉ๊ธ์ ์์ Co๋ณด๋ค ์ต๋ 200% ๋์ ํญ๋ณต ์ ์ (breakdown voltage)์ ๋ณด์๋ค.
๋ฐ๋์ฒด ๋ฐฐ์ ๊ณต์ ์ ์ ์ฉํ ์ ์๋ Cr ๋ํ ๋๋์ ์ด์ฒ๋ฆฌ ์กฐ๊ฑด์ ์ํฅ์ ํ์ธํ์๋ค. Cr์ด 1at% ๋ฏธ๋ง์ผ๋ก ๋ํ๋์์ ๋ ์ฐ์ํ ์ ๊ธฐ์ ์ ๋ขฐ์ฑ์ ๋ํ๋ด์๋ค. ๋ํ, 250โ ์ด์์์ 30๋ถ ์ด์ ์ด์ฒ๋ฆฌ๋ฅผ ํ์์ ๋ Cr2O3 ๊ณ๋ฉด์ธต์ด ํ์ฑ๋จ์ ์ ์ ์์๋ค. ์ฆ, ํ์ฌ ๋ฐฐ์ ๊ณต์ ์จ๋๊ฐ 400ยฐC ๋ฏธ๋ง์ด๊ธฐ ๋๋ฌธ์ Co-Cr ํฉ๊ธ์ด ๋ฐฐ์ ๊ณต์ ์ ์ ์ฉ ๊ฐ๋ฅํจ์ ํ์ธํ์๋ค. TDDB ์๋ช
ํ
์คํธ๋ ์ํ๋์์ผ๋ฉฐ Co-Cr ํฉ๊ธ ๋ฐฐ์ ์ ์์ฒด ํ์ฑ๋ ๊ณ๋ฉด์ธต์ ๋งค์ฐ ์์ ์ ์ธ ํ์ฐ ์ฅ๋ฒฝ ํน์ฑ์ ๋ณด์ฌ์ฃผ์๋ค. DFT ๋ถ์์ Cr2O3์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง์ด ํ์ฌ ์ฐ๊ตฌ๋๊ณ ์๋ TiN ํ์ฐ ์ฅ๋ฒฝ๋ณด๋ค ๋ ๋์ ์๋์ง ์ฅ๋ฒฝ ๊ฐ์ ๋ณด์ฌ์ฃผ๊ธฐ ๋๋ฌธ์ ๋งค์ฐ ์ ๋งํ ํ์ฐ๋ฐฉ์ง๋ง์์ ๋ณด์ฌ์ฃผ์๋ค.
๋ณธ ์ฐ๊ตฌ๋ ๋ฐ๋์ฑ ๋ฐฐ์ ๋ฌผ์ง ์์คํ
์์ ์ฑ๋ฅ๊ณผ ์ ๋ขฐ์ฑ์ ๊ณ ๋ คํ ์ด์ญํ์ ๊ณ์ฐ์ ํตํด Co ๊ธฐ๋ฐ ์๊ฐํ์ฑ ํ์ฐ๋ฐฉ์ง๋ง์ ์ค๊ณํ์๋ค. ์คํ ๊ฒฐ๊ณผ ์ ๋ขฐ์ฑ์ด ์ฐ์ํ๊ณ ์์ฃผ ์์ Cr2O3 ํ์ฐ๋ฐฉ์ง๋ง์ด ์๋ Co-Cr ํฉ๊ธ์ด ์ ์ํ์๋ค. ๋ฌผ์ง ์ค๊ณ์ ์ ๊ธฐ์ ์ ๋ขฐ์ฑ ๊ฒ์ฆ์ Co/Cr2O3/SiO2 ๋ฌผ์ง ์์คํ
์ ์ ์ํ์๊ณ ์์ผ๋ก์ ๋ค๊ฐ์ฌ ์ฐจ์ธ๋ ๋ฐฐ์ ์์ ๊ตฌํ๋ ์ ์์ ๊ฒ์ผ๋ก ๊ธฐ๋๋๋ค.Abstract i
Table of Contents v
List of Tables ix
List of Figures xii
Chapter 1. Introduction 1
1.1. Scaling down of VLSI systems 1
1.2. Driving force of interconnect system evolution 7
1.3. Driving force of beyond Cu interconnects 11
1.4. Objective of the thesis 18
1.5. Organization of the thesis 21
Chapter 2. Theoretical Background 22
2.1. Evolution of interconnect systems 22
2.1.1. Cu/barrier/low-k interconnect system 22
2.1.2. Process developments for interconnect reliability 27
2.1.3. 3rd generation of interconnect system 31
2.2 Thermodynamic tools for Co self-forming barrier 42
2.2.1 Binary phase diagram 42
2.2.2 Ellingham diagram 42
2.2.3 Activity coefficient 43
2.3. Reliability of Interconnects 45
2.3.1. Current conduction mechanisms in dielectrics 45
2.3.2. Reliability test vehicles 50
2.3.3. Dielectric breakdown assessment 52
2.3.4. Dielectric breakdown mechanisms 55
2.3.5. Reliability test: VRDB and TDDB 56
2.3.6. Lifetime models 57
Chapter 3. Experimental Procedures 60
3.1. Thin film deposition 60
3.1.1. Substrate preparation 60
3.1.2. Oxidation 61
3.1.3. Co alloy deposition using DC magnetron sputtering 61
3.1.4. Annealing process 65
3.2. Thin film characterization 67
3.2.1. Sheet resistance 67
3.2.2. X-ray photoelectron spectroscopy (XPS) 68
3.3. Metal-Insulator-Semiconductor (MIS) device fabrication 70
3.3.1. Patterning using lift-off process 70
3.3.2. TDDB packaging 72
3.4. Reliability analysis 74
3.4.1. Electrical reliability analysis 74
3.4.2. Transmission electron microscopy (TEM) analysis 75
3.5. Computation 76
3.5.1 FactsageTM calculation 76
3.5.2. Density Functional Theory (DFT) calculation 77
Chapter 4. Co Alloy Design for Advanced Interconnects 78
4.1. Material design of Co alloy self-forming barrier 78
4.1.1. Rule of thumb of Co-X alloy 78
4.1.2. Co alloy phase 80
4.1.3. Out-diffusion stage 81
4.1.4. Reaction step with SiO2 dielectric 89
4.1.5. Comparison criteria 94
4.2. Comparison of Co alloy candidates 97
4.2.1. Thin film resistivity evaluation 97
4.2.2. Self-forming behavior using XPS depth profile analysis 102
4.2.3. MIS device reliability test 110
4.3 Summary 115
Chapter 5. Co-Cr Alloy Interconnect with Robust Self-Forming Barrier 117
5.1. Compatibility of Co-Cr alloy SFB process 117
5.1.1. Effect of Cr doping concentration 117
5.1.2. Annealing process condition optimization 119
5.2. Reliability of Co-Cr interconnects 122
5.2.1. VRDB quality test with Co-Cr alloys 122
5.2.2. Lifetime evaluation using TDDB method 141
5.2.3. Barrier mechanism using DFT 142
5.3. Summary 145
Chapter 6. Conclusion 148
6.1. Summary of results 148
6.2. Research perspectives 150
References 151
Abstract (In Korean) 166
Curriculum Vitae 169๋ฐ
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