Random Routing and Concentration in Quantum Switching Networks

Flexible distribution of data in the form of quantum bits or qubits among spatially separated entities is an essential component of envisioned scalable quantum computing architectures. Accordingly, we consider the problem of dynamically permuting groups of quantum bits, i.e., qubit packets, using networks of reconfigurable quantum switches. We demonstrate and then explore the equivalence between the quantum process of creation of packet superpositions and the process of randomly routing packets in the corresponding classical network. In particular, we consider an n × n Baseline network for which we explicitly relate the pairwise input-output routing probabilities in the classical random routing scenario to the probability amplitudes of the individual packet patterns superposed in the quantum output state. We then analyze the effect of using quantum random routing on a classically non-blocking configuration like the Benes network. We prove that for an n × n quantum Benes network, any input packet assignment with no output contention is probabilistically self-routable. In particular, we prove that with random routing on the first (log n-1) stages and bit controlled self-routing on the last log n stages of a quantum Benes network, the output packet pattern corresponding to routing with no blocking is always present in the output quantum state with a non-zero probability. We give a lower bound on the probability of observing such patterns on measurement at the output and identify a class of 2n-1 permutation patterns for which this bound is equal to 1, i.e., for all the permutation patterns in this class the following is true: in every pattern in the quantum output assignment all the valid input packets are present at their correct output addresses. In the second part of this thesis we give the complete design of quantum sparse crossbar concentrators. Sparse crossbar concentrators are rectangular grids of simple 2 × 2 switches or crosspoints, with the switches arranged such that any k inputs can be connected to some k outputs. We give the design of the quantum crosspoints for such concentrators and devise a self-routing method to concentrate quantum packets. Our main result is a rigorous proof that certain crossbar structures, namely, the fat-slim and banded quantum crossbars allow, without blocking, the realization of all concentration patterns with self-routing. In the last part we consider the scenario in which quantum packets are queued at the inputs to an n × n quantum non-blocking switch. We assume that each packet is a superposition of m classical packets. Under the assumption of uniform traffic, i.e., any output is equally likely to be accessed by a packet at an input we find the minimum value of m such that the output quantum state contains at least one packet pattern in which no two packets contend for the same output. Our calculations show that for m=9 the probability of a non-contending output pattern occurring in the quantum output is greater than 0.99 for all n up to 64

Size bounds and parallel algorithms for networks

SIGLEAvailable from British Library Document Supply Centre- DSC:D34009/81 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Analysis and Optimization of the Scheffler Solar Concentrator

The Scheffler reflector is a new solar concentrator design which maintains a fixed focus while only having a single axis tracking mechanism. This design makes the construction and operation of high temperature solar concentrators accessible to developing nations. In this project, I wrote computer simulation codes to better understand the dynamics and the effect of deformation or deviations from ideal conditions in order to define necessary manufacturing and operational tolerances. These tools and knowledge drove the prototyping of new reflector concepts by myself and other students on my team. A fiberglass prototype was able to drive the cost of a reflector to sub-$50 and a wood reflector was manufactured with accessible materials and techniques used in boat building

Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

Generic low power reconfigurable distributed arithmetic processor

Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronic and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. For modern systems, more energy is required to support the powerful computational capability which accords with the increasing requirements, and these requirements cause the change of standards not only in audio and video broadcasting but also in communication such as wireless connection and network protocols. Powerful flexibility and low consumption are repellent, but their combination in one system is the ultimate goal of designers. A generic domain-specific low-power reconfigurable processor for the distributed arithmetic algorithm is presented in this dissertation. This domain reconfigurable processor features high efficiency in terms of area, power and delay, which approaches the performance of an ASIC design, while retaining the flexibility of programmable platforms. The architecture not only supports typical distributed arithmetic algorithms which can be found in most still picture compression standards and video conferencing standards, but also offers implementation ability for other distributed arithmetic algorithms found in digital signal processing, telecommunication protocols and automatic control. In this processor, a simple reconfigurable low power control unit is implemented with good performance in area, power and timing. The generic characteristic of the architecture makes it applicable for any small and medium size finite state machines which can be used as control units to implement complex system behaviour and can be found in almost all engineering disciplines. Furthermore, to map target applications efficiently onto the proposed architecture, a new algorithm is introduced for searching for the best common sharing terms set and it keeps the area and power consumption of the implementation at low level. The software implementation of this algorithm is presented, which can be used not only for the proposed architecture in this dissertation but also for all the implementations with adder-based distributed arithmetic algorithms. In addition, some low power design techniques are applied in the architecture, such as unsymmetrical design style including unsymmetrical interconnection arranging, unsymmetrical PTBs selection and unsymmetrical mapping basic computing units. All these design techniques achieve extraordinary power consumption saving. It is believed that they can be extended to more low power designs and architectures. The processor presented in this dissertation can be used to implement complex, high performance distributed arithmetic algorithms for communication and image processing applications with low cost in area and power compared with the traditional methods

The brazilian telecommunications industry: accumulation of microelectronic technology in the manufacturing and service sectors

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Study of multi-megawatt technology needs for photovoltaic space power systems, volume 2

Possible missions requiring multimegawatt photovoltaic space power systems in the 1990's time frame and power system technology needs associated with these missions are examined. Four specific task areas were considered: (1) missions requiring power in the 1-10 megawatt average power region; (2) alternative power systems and component technologies; (3) technology goals and sensitivity trades and analyses; and (4) technology recommendations. Specific concepts for photovoltaic power approaches considered were: planar arrays, concentrating arrays, hybrid systems using Rankine engines, thermophotovoltaic approaches; all with various photovoltaic cell component technologies. Various AC/DC power management approaches, and battery, fuel cell, and flywheel energy storage concepts are evaluated. Interactions with the electrical ion engine injection and stationkeeping system are also considered

The simulation and optimization of steady state process circuits by means of artificial neural networks

Dissertation (Ph.D.) -- University of Stellenbosch, 1993.ENGLISH ABASTRACT: Since the advent of modern process industries engineers engaged in the modelling and simulation of chemical and metallurgical processes have had to contend with two important dilemmas. The first concerns the ill-defined nature of the processes they have to describe, while the second relates to the limitations of prevailing computational resources. Current process simulation procedures are based on explicit process models in one form or another. Many chemical and metallurgical processes are not amenable to this kind of modelling however, and can not be incorporated effectively into current commercial process simulators. As a result many process operations do not benefit from the use of predictive models and simulation routines and plants are often poorly designed and run, ultimately leading to considerable losses in revenue. In addition to this dilemma, process simulation is in a very real way constrained by available computing resources. The construction of adequate process models is essentially meaningless if these models can not be solved efficiently - a situation occurring all too often. In the light of these problems, it is thus not surprising that connectionist systems or neural network methods are singularly attractive to process engineers, since they provide a powerful means of addressing both these dilemmas. These nets can form implicit process models through learning by example, and also serve as a vehicle for parallel supercomputing devices. In this dissertation the use of artificial neural networks for the steady state modelling and optimization of chemical and metallurgical process circuits is consequently investigated. The first chapter is devoted to a brief overview of the simulation of chemical and metallurgical plants by conventional methods, as well as the evolution and impact of computer technology and artificial intelligence on the process industries. Knowledge of the variance covariance matrices of process data is of paramount importance to data reconciliation and gross error detection problems, and although various methods can be employed to estimate these often unknown variances, it is shown in the second chapter that the use of feedforward neural nets can be more efficient than conventional strategies. In the following chapter the important problem of gross error detection in process data is addressed. Existing procedures are statistical and work well for systems subject to linear constraints. Non-linear constraints are not handled well by these methods and it is shown that back propagation neural nets can be trained to detect errors in process systems, regardless of the nature of the constraints. In the fourth chapter the exploitation of the massively parallel information processing structures of feedback neural nets in the optimization of process data reconciliation problems is investigated. Although effective and sophisticated algorithms are available for these procedures, there is an ever present demand for computational devices or routines that can accommodate progressively larger or more complex problems. Simulations indicate that neural nets can be efficient instruments for the implementation of parallel strategies for the optimization of such problems. In the penultimate chapter a gold reduction plant and a leach plant are modelled with neural nets and the models shown to be considerably better than the linear regression models used in practice. The same technique is also demonstrated with the modelling of an apatite flotation plant. Neural nets can also be used in conjunction with other methods and in the same chapter the steady state simulation and optimization of a gravity separation circuit with the use of two linear programming models and a neural net are described.AFRIKAANSE OPSOMMING: Sedert die ontstaan van prosesingenieurswese, het ingenieurs gemoeid met die modellering en simulasie van chemiese en metallurgiese prosesse met twee belangrike dilemmas te kampe gehad. Die eerste het te make met die swakgedefinieerde aard van chemiese prosesse, wat die beskrywing en dus ook die beheer daarvan kompliseer, terwyl die tweede verband hou met die beperkinge van huidige berekeningsmiddele. Die prosesse wat tans gebruik word om chemiese prosesse te simuleer is gebaseer op eksplisiete prosesmodelle van een of ander aard. Baie chemiese en metallurgiese prosesse kan egter nie op 'n eksplisiete wyse gemodelleer word nie, en kan gevolglik ook nie doeltreffendheid deur kommersiële prosessimulators beskryf word nie. Die bedryf van baie prosesse vind derhalwe nie baat by die gebruik van voorspellende modelle en simulasie-algoritmes nie en aanlegte word dikwels suboptimaal ontwerp en bedryf, wat uiteindelik tot aansienlike geldelike verliese kan lei. Prosessimulasie word op die koop toe ook beperk deur die beskikbaarheid van berekeningsfasiliteite. Die konstruksie van geskikte prosesmodelle hou geen voordeel in as hierdie modelle nie doeltreffendheid opgelos kan word nie. Teen die agtergrond van hierdie probleme is dit nie verrassend dat neurale netwerke 'n besondere bekoring vir prosesingenieurs inhou nie, aangesien hulle beide hierdie dilemmas aanspreek. Hierdie nette kan implisiete prosesmodelle konstrueer deur te leer van voorbeelde en dien ook as 'n raamwerk vir parallelle superrekenaars. In hierdie proefskrif word die gebruik van kunsmatige neurale netwerke vir gestadigde toestandsmodellering en optimering van chemiese en metallurgiese prosesse gevolglik ondersoek. Die eerste hoofstuk word gewy aan 'n kort oorsig oor die simulasie van chemiese en metallurgiese aanlegte met konvensionele tegnieke, asook die ontwikkeling en impak van rekenaartegnologie en skynintelligensie in die prosesnywerhede. Kennis van die variansie-kovariansie-matrikse van prosesdata is van kardinale belang vir datarekonsiliasie en die identifikasie en eliminasie van sistematiese foute en alhoewel verskeie metodes aangewend kan word om hierdie onbekende variansies te beraam, word daar in die tweede hoofstuk getoon dat die gebruik van neurale netwerke meer doeltreffend is as konvensionele strategieë. In die volgende hoofstuk word die belangrike probleem van sistematiese foutopsporing in prosesdata ondersoek. Bestaande prosedures is statisties van aard en werk goed vir stelsels onderworpe aan lineêre beperkinge. Nie-lineêre beperkinge kan nie doeltreffend deur hierdie prosedures hanteer word nie en daar word gewys dat terugwaarts-propagerende nette geleer kan word om sulke foute in prosessisteme op te spoor, ongeag die aard van die beperkinge. In die vierde hoofstuk word die rekonsiliasie van prosesdata met behulp van massiewe parallelle dataverwerkingstrukture soos verteenwoordig deur terugvoerende neurale nette, ondersoek. Alhoewel doeltreffende en gesofistikeerde algoritmes beskikbaar is vir die optimering van die tipe probleme, is daar 'n onversadigbare aanvraag na rekenaars wat groter en meer komplekse stelsels kan akkommodeer. Simulasie dui aan dat neurale nette effektief aangewend kan word vir die implementering van parallelle strategieë vir dié tipe optimeringsprobleme. In die voorlaaste hoof stuk word die konneksionistiese modellering van 'n goudreduksie- en 'n logingsaanleg beskryf en daar word aangetoon dat die neurale netwerk-modelle aansienlik beter resultate lewer as die linneêre regressie modelle wat in die praktyk gebruik word. Dieselfde tegnieke vir die modellering van 'n flottasie-aanleg vir apatiet word ook bespreek. Neural nette kan ook saam met ander metodes aangewend word en in dieselfde hoofstuk word die gebruik van twee lineêre programmeringsmodelle en 'n neural net om 'n gravitasieskeidingsbaan onder gestadigde toestande te simuleer en te optimeer, beskryf

Neural networks-on-chip for hybrid bio-electronic systems

PhD ThesisBy modelling the brains computation we can further our understanding of its function and develop novel treatments for neurological disorders. The brain is incredibly powerful and energy e cient, but its computation does not t well with the traditional computer architecture developed over the previous 70 years. Therefore, there is growing research focus in developing alternative computing technologies to enhance our neural modelling capability, with the expectation that the technology in itself will also bene t from increased awareness of neural computational paradigms. This thesis focuses upon developing a methodology to study the design of neural computing systems, with an emphasis on studying systems suitable for biomedical experiments. The methodology allows for the design to be optimized according to the application. For example, di erent case studies highlight how to reduce energy consumption, reduce silicon area, or to increase network throughput. High performance processing cores are presented for both Hodgkin-Huxley and Izhikevich neurons incorporating novel design features. Further, a complete energy/area model for a neural-network-on-chip is derived, which is used in two exemplar case-studies: a cortical neural circuit to benchmark typical system performance, illustrating how a 65,000 neuron network could be processed in real-time within a 100mW power budget; and a scalable highperformance processing platform for a cerebellar neural prosthesis. From these case-studies, the contribution of network granularity towards optimal neural-network-on-chip performance is explored