Ultra-Low-Power Superconductor Logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.Comment: 7 pages, 5 figure

An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System

Incorporating speed probability distribution to the computation of the route planning in car navigation systems guarantees more accurate and precise responses. In this paper, we propose a novel approach for dynamically selecting the number of samples used for the Monte Carlo simulation to solve the Probabilistic Time-Dependent Routing (PTDR) problem, thus improving the computation efficiency. The proposed method is used to determine in a proactive manner the number of simulations to be done to extract the travel-time estimation for each specific request while respecting an error threshold as output quality level. The methodology requires a reduced effort on the application development side. We adopted an aspect-oriented programming language (LARA) together with a flexible dynamic autotuning library (mARGOt) respectively to instrument the code and to take tuning decisions on the number of samples improving the execution efficiency. Experimental results demonstrate that the proposed adaptive approach saves a large fraction of simulations (between 36% and 81%) with respect to a static approach while considering different traffic situations, paths and error requirements. Given the negligible runtime overhead of the proposed approach, it results in an execution-time speedup between 1.5x and 5.1x. This speedup is reflected at infrastructure-level in terms of a reduction of around 36% of the computing resources needed to support the whole navigation pipeline

Operational characteristics of surge arresters within high voltage substations

Surge arresters form a critical component in the safe and reliable operation of electrical zone substations. Overvoltages resulting from a lightning strike pose the greatest risk of damage to substation equipment reaching peak values of over 100 times the nominal line voltage within microseconds. During such overvoltage events, the surge arrester limits the level of voltage that the equipment is subjected to, thus providing protection to very expensive, and specialised electrical infrastructure. Correct arrester specification is the first step in determining the type of surge arrester required for each installation. A second, but no less important step is determination of its physical location and connection method. The distance a surge arrester is located from equipment is a significant factor in its ability in protecting equipment. Through the undertaking of this detailed research project, optimum arrester location, connection methods and insulation co-ordination derived from software simulation will be compared to standard design principles utilised by Essential Energy (EE) and verified using equivalent circuit analysis

Single event upset hardened CMOS combinational logic and clock buffer design

A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate

Multipath Routing in VANET: Multi-Agent based Approach

In VANET routing of data is a exciting task owing to the high dynamics involved in this network. Delivery of data to the projected destination turns out to be very puzzling. Single path routing suffers from drawbacks like unreliability and etc. To manage such situation multipath data delivery is very nominal. In multipath routing more than one path discovered between source and destination node. Data packet can be sent simultaneously in all paths or data packet can be send by selecting path one after another. It is up to the routing algorithm to select path thoughtfully to deliver data proficiently. However existing multipath routing protocols even though compute multipath, only one path will be engaged in actual communication at any given time. Hence this work proposes Multipath Routing in VANET: Multi-agent based Approach which calculates multiple paths amongst source and destination. Further, all such computed paths will be employed for information dissemination. NS2 simulation of the proposed approach in realistic mobility models show that it can select more stable link and improve the network performance

Adaptive Mechanisms to Improve Message Dissemination in Vehicular Networks

En el pasado, se han dedicado muchos recursos en construir mejores carreteras y autovías. Con el paso del tiempo, los objetivos fueron cambiando hacia las mejoras de los vehículos, consiguiendo cada vez vehículos más rápidos y con mayor autonomía. Más tarde, con la introducción de la electrónica en el mercado del automóvil, los vehículos fueron equipados con sensores, equipos de comunicaciones, y otros avances tecnológicos que han permitido la aparición de coches más eficientes, seguros y confortables. Las aplicaciones que nos permite el uso de las Redes Vehiculares (VNs) en términos de seguridad y eficiencia son múltiples, lo que justifica la cantidad y recursos de investigación que se están dedicando en los últimos años. En el desarrollo de esta Tesis, los esfuerzos se han centrado en el área de las Vehicular Ad-hoc Networks, una subclase de las Redes Vehiculares que se centra en las comunicaciones entre los vehículos, sin necesidad de que existan elementos de infraestructura. Con la intención de mejorar el proceso de diseminación de mensajes de alerta, imprescindibles para las aplicaciones relacionadas con la seguridad, se ha propuesto un esquema de difusión adaptativo, capaz de seleccionar automáticamente el mecanismo de difusión óptimo en función de la complejidad del mapa y de la densidad actual de vehículos. El principal objetivo es maximizar la efectividad en la difusión de mensajes, reduciendo al máximo el número de mensajes necesarios, evitando o mitigando las tormentas de difusión. Las propuestas actuales en el área de las VANETs, se centran principalmente en analizar escenarios con densidades típicas o promedio. Sin embargo, y debido a las características de este tipo de redes, a menudo se dan situaciones con densidades extremas (altas y bajas). Teniendo en cuenta los problemas que pueden ocasionar en el proceso de diseminación de los mensajes de emergencia, se han propuesto dos nuevos esquemas de difusión para bajas densidades: el \emph{Junction Store and Forward} (JSF) y el \emph{Neighbor Store and Forward} (NSF). Además, para situaciones de alta densidad de vehículos, se ha diseñado el \emph{Nearest Junction Located} (NJL), un esquema de diseminación que reduce notablemente el número de mensajes enviados, sin por ello perder prestaciones. Finalmente, hemos realizado una clasificacion de los esquemas de difusión para VANETs más importantes, analizando las características utilizadas en su diseño. Además hemos realizado una comparación de todos ellos, utilizando el mismo entorno de simulación y los mismos escenarios, permitiendo conocer cuál es el mejor esquema de diseminación a usar en cada momento

Using Fine Grain Approaches for highly reliable Design of FPGA-based Systems in Space

Nowadays using SRAM based FPGAs in space missions is increasingly considered due to their flexibility and reprogrammability. A challenge is the devices sensitivity to radiation effects that increased with modern architectures due to smaller CMOS structures. This work proposes fault tolerance methodologies, that are based on a fine grain view to modern reconfigurable architectures. The focus is on SEU mitigation challenges in SRAM based FPGAs which can result in crucial situations