Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date