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Development of advanced digital techniques for data acquisition processing and communication Interim scientific report
Design, video data characteristics, error control, and compression algorithms for Mars television mapping missio
SRAM PUF์ ์ ๋ขฐ์ฑ ๊ฐ์ ์ ์ํ ์ ์ ๊ณต๊ธ ๊ธฐ๋ฒ
ํ์๋
ผ๋ฌธ (์์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ์ตํฉ๊ณผํ๊ธฐ์ ๋ํ์ ์ตํฉ๊ณผํ๋ถ(์ง๋ฅํ์ตํฉ์์คํ
์ ๊ณต), 2021. 2. ์ ๋์.PUF (Physically Unclonable Function)์ ํ๋์จ์ด ๋ ๋ฒจ์ ์ธ์ฆ ๊ณผ ์ ์์ ๋๋ฆฌ ์ด์ฉ๋๋ ๋ฐฉ๋ฒ์ด๋ค. ๊ทธ ์ค์์๋ SRAM PUF๋ ๊ฐ์ฅ ์ ์ ๋ ค์ง PUF์ ๋ฐฉ๋ฒ๋ก ์ด๋ค. ๊ทธ๋ฌ๋ ์์ธก ๋ถ๊ฐ๋ฅํ ๋์์ผ๋ก ์ธํด ๋ฐ์๋๋ ๋ฎ์ ์ฌ์์ฐ์ฑ๊ณผ ์ ์ ๊ณต๊ธ ๊ณผ์ ์์ ๋ฐ์ํ๋ ๋
ธ์ด์ฆ์ ๋ฌธ์ ๋ฅผ ๊ฐ์ง๊ณ ์๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ ํจ๊ณผ์ ์ผ๋ก SRAM PUF์ ์ฌ์์ฐ์ฑ์ ํฅ์์ํฌ ์ ์๋ ๋ ๊ฐ์ง ์ ์ ๊ณต๊ธ ๊ธฐ๋ฒ์ ์ ์ํ๋ค. ์ ์ํ ๊ธฐ๋ฒ๋ค์ ๊ฐ์ด ์ฐ์ถ๋ ๋ ์์ญ ํน์ ์ ์ ๊ณต๊ธ์์ ๊ธฐ์ธ๊ธฐ(ramp-up ์๊ฐ)๋ฅผ ์กฐ์ ํจ์ผ๋ก์จ ์ ํ์ง ์๋ ๋นํธ์ ๋ค์งํ(flipping) ํ์์ ์ค์ธ๋ค. 180nm ๊ณต์ ์ผ๋ก ์ ์๋ ํ
์คํธ ์นฉ์ ์ด์ฉํ ์ธก์ ๊ฒฐ๊ณผ ์ฌ์์ฐ์ฑ์ด 2.2๋ฐฐ ํฅ์๋์์ ๋ฟ๋ง ์๋๋ผ NUBs(Native Unstable Bits)๋ 54.87% ๊ทธ๋ฆฌ๊ณ BER (Bit Error Rate)๋ 55.05% ๊ฐ์ํ ๊ฒ์ ํ์ธํ์๋ค.Physically unclonable function (PUF) is a widely used hardware-level identification method. SRAM-based PUFs are the most well-known PUF topology, but they typically suffer from low reproducibility due to non-deterministic behaviors and noise during power-up process. In this work, we propose two power-up control techniques that effectively improve reproducibility of the SRAM PUFs. The techniques reduce undesirable bit flipping during evaluation by controlling either evaluation region or power supply ramp-up speed. Measurement results from the 180 nm test chip confirm that native unstable bits (NUBs) are reduced by 54.87% and bit error rate (BER) decreases by 55.05% while reproducibility increases by 2.2ร.Chapter 1 Introduction 1
1.1 PUF in Hardware Securit 1
1.2 Prior Works and Motivation 2
Chapter 2 Related works and Motivation 5
2.1 Uniqueness 7
2.2 Reproducibility 7
2.3 Hold Static Noise Margin (SNM) 8
2.4 Bit Error Rate (BER) 9
2.5 PUF Static Noise Margin Ratio (PSNMratio) 9
Chapter 3 Microarchitecture-Aware Code Generation 11
3.1 Scheme 1: Developing Fingerprint in Sub-Threshold Region 13
3.2 Scheme 2: Controlling Voltage Ramp-up Speed 17
Chapter 4 Experimental Evaluation 19
4.1 Experimental Setup 19
4.2 Evaluation Results 21
Chapter 5 Conclusion 28
Bibliography 29
Abstract in Korean 33Maste
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Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security.
In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented
็ฉ็่ค่ฃฝไธ่ฝ้ขๆฐใซใใใๅฎๅ จๆงใฎ่ฉไพกใจๅไธใซ้ขใใ็ ็ฉถ
In this thesis, we focus on Physically Unclonable Functions (PUFs), which are expected as one of the most promising cryptographic primitives for secure chip authentication. Generally, PUFbased authentication is achieved by two approaches: (A) using a PUF itself, which has multiple challenge (input) and response (output) pairs, or (B) using a cryptographic function, the secret key of which is generated from a PUF with a single challenge-response pair (CRP). We contribute to:(1) evaluate the security of Approach (A), and (2) improve the security of Approach (B). (1) Arbiter-based PUFs were the most feasible type of PUFs, which was used to construct Approach (A). However, Arbiter-based PUFs have a vulnerability; if an attacker knows some CRPs, she/he can predict the remaining unknown CRPs with high probability. Bistable Ring PUF (BR-PUF) was proposed as an alternative, but has not been evaluated by third parties. In this thesis, in order to construct Approach (A) securely, we evaluate the difficulty of predicting responses of a BR-PUF experimentally. As a result, the same responses are frequently generated for two challenges with small Hamming distance. Also, particular bits of challenges have a great impact on the responses. In conclusion, BR-PUFs are not suitable for achieving Approach (A)securely. In future work, we should discuss an alternative PUF suitable for secure Approach (A).(2) In order to achieve Approach (B) securely, a secret key ? generated from a PUF response?should have high entropy. We propose a novel method of extracting high entropy from PUF responses. The core idea is to effectively utilize the information on the proportion of โ1โs including in repeatedly-measured PUF responses. We evaluate its effectiveness by fabricated test chips. As a result, the extracted entropy is about 1.72 times as large as that without the proposed method.Finally, we organize newly gained knowledge in this thesis, and discuss a new application of PUF-based technologies.้ปๆฐ้ไฟกๅคงๅญฆ201
Design and Evaluation of FPGA-based Hybrid Physically Unclonable Functions
A Physically Unclonable Function (PUF) is a new and promising approach to provide security for physical systems and to address the problems associated with traditional approaches. One of the most important performance metrics of a PUF is the randomness of its generated response, which is presented via uniqueness, uniformity, and bit-aliasing. In this study, we implement three known PUF schemes on an FPGA platform, namely SR Latch PUF, Basic RO PUF, and Anderson PUF. We then perform a thorough statistical analysis on their performance. In addition, we propose the idea of the Hybrid PUF structure in which two (or more) sources of randomness are combined in a way to improve randomness. We investigate two methods in combining the sources of randomness and we show that the second one improves the randomness of the response, significantly. For example, in the case of combining the Basic RO PUF and the Anderson PUF, the Hybrid PUF uniqueness is increased nearly 8%, without any pre-processing or post-processing tasks required. Two main categories of applications for PUFs have been introduced and analyzed: authentication and secret key generation. In this study, we introduce another important application for PUFs. In fact, we develop a secret sharing scheme using a PUF to increase the information rate and provide cheater detection capability for the system. We show that, using the proposed method, the information rate of the secret sharing scheme will improve significantly
Design of Discrete-time Chaos-Based Systems for Hardware Security Applications
Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices
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