Design, Extraction, and Optimization Tool Flows and Methodologies for Homogeneous and Heterogeneous Multi-Chip 2.5D Systems

Chip and packaging industries are making significant progress in 2.5D design as a result of increasing popularity of their application. In advanced high-density 2.5D packages, package redistribution layers become similar to chip Back-End-of-Line routing layers, and the gap between them scales down with pin density improvement. Chiplet-package interactions become significant and severely affect system performance and reliability. Moreover, 2.5D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. This thesis presents chiplet-package cross-boundary design, extraction, analysis, and optimization tool flows and methodologies for high-density 2.5D packaging technologies. A holistic flow is presented that can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Several design techniques are demonstrated for agile development and quick turn-around time. To validate the flow in silicon, a chip was taped out and studied in TSMC 65nm technology. As the holistic flow cannot handle heterogeneous technologies, in-context flows are presented. Three different flavors of the in-context flow are presented, which offer trade-offs between scalability and accuracy in heterogeneous 2.5D system designs. Inductance is an inseparable part of a package design. A holistic flow is presented that takes package inductance into account in timing analysis and optimization steps. Custom CAD tools are developed to make these flows compatible with the industry standard tools and the foundry model. To prove the effectiveness of the flows several design cases of an ARM Cortex-M0 are implemented for comparitive study

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Scale up of advanced packaging and system integration for hybrid technologies

This paper presents an overview of challenges in system integration for 2.5D/3D assemblies, including copackaged optics and electronics, MEMS and microfluidics. It addresses the gap between early-stage prototypes and volume manufacturing that need true advanced packaging and system integration to realize their complex multi-technology devices. This is done by means of a virtual demonstrator that include both 2.5D/3D assemblies of ASICs and integrated photonic devices, as well as MEMS and microfluidics devices. It also addresses lowering the cost barrier for users accessing these technologies for their products, such that it will enable an increased uptake of system integration by the industry at large

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Integrated silicon photonic packaging

Silicon photonics has garnered plenty of interests from both the academia and industry due to its high-speed transmission potential as well as sensing capability to complement silicon electronics. This has led to significant growth on the former, valuing at US$626.8M in 2017 and is expected to grow 3-fold to US$ 1,988.2M by 2023, based on data from MarketsandMarkets™. Silicon photonics’ huge potential has led to worldwide attention on fundamental research, photonic circuit designs and device fabrication technologies. However, as with silicon electronics in its early years, the silicon photonics industry today is extremely fragmented with various chip designs and layouts. Most silicon photonic devices fabricated are not able to reach the hand of consumers, due to a lack of information related to packaging design rules, components and processes. The importance of packaging technologies, which play a crucial role in turning photonic circuits and devices into the final product that end users can used in their daily lives, has been overlooked and understudied. This thesis aims to – 1. fill the missing gap by adapting existing electronics packaging techniques, 2. assess its scalability, 3. assess supply chain integration and finally 4. develop unique packaging approaches specifically for silicon photonics. The first section focused on high density packaging components and processes using University of California, Berkeley’s state-of-the-art silicon photonic MEMS optical switches as test devices. Three test vehicles were developed using (1) via-less ceramic and (2) spring-contacted electrical interposers for 2D integration and (3) through-glass-via electrical interposers for 2.5D heterogeneous integration. A high density (1) lidless fibre array and (2) a 2D optical interposer, which allows pitch-reduction of optical waveguides were also developed in this thesis. Together, these components demonstrated the world’s first silicon 2 photonic MEMS optical switch package and subsequently the highest density silicon photonic packaging components with 512 electrical I/Os and 272 optical I/Os. The second section then moved away from active optical coupling that was used in the former, investigating instead passive optical packaging concepts for the future. Two approaches were investigated - (1) grating-to-grating and (2) evanescent couplings. The former allows the development of pluggable packages, separating fibre coupling away from the device while the latter allows simultaneous optical and electrical packaging on a glass wafer in a single process. Lastly, the knowhow and concepts developed in this thesis were compiled into packaging design rules and subsequently introduced into H2020-MORPHIC, PIXAPP packaging training courses (as a trainer) and other packaging projects within the group

Modeling, Design and Demonstration of 1 µm Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications

Since 2010, heterogeneous integration (HI) of multiple integrated circuits (ICs) on to a package substrate has become one of the most popular solutions to improve system performance and miniaturization. This HI has emerged to continue Moore’s Law scaling to support high performance computing (HPC) applications such as artificial intelligence, autonomous driving, 5G, cloud computing and wearable devices. Package substrate technology has only just begun to become a huge enabler to system scaling, beyond Moore’s Law, in terms of overall miniaturization, high bandwidth performance and high density of interconnections between heterogeneous dies to enable more operations per second. Redistribution layer (RDL) technology is the main component to interconnecting these ICs on a single package to scale beyond Moore’s Law. Examining RDL technology further it is observed that only back-end-of-line (BEOL) RDL fabricated on silicon can provide the interconnections needed for a high-performance system. However, this technology has reached a fundamental limitation due to the high resistance and capacitance of BEOL RDL that limits the further scaling of system performance. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 1µm and beyond. This research focuses on addressing these challenges by: (A) Electrical Design and Modeling of multi-layer polymer RDL for 4x lower resistance and 4x higher bandwidth than silicon BEOL RDL, (B) Design and demonstration of novel photoresist materials for scaling of polymer RDL well below 1µm using low-cost large panel-based tools and processes, (C) Fundamental evaluation of current substrate integration impacts on the novel photoresist material developed for scaling of polymer RDL, (D) Scaling of the semi-additive process (SAP) that is utilized in the panel-based RDL through fundamental material and process innovations.Ph.D