Landslide inventories for climate impacts research in the European Alps

Author's manuscript version. The final published article is available from the publisher via: doi:10.1016/j.geomorph.2014.09.005Copyright © 2014 Elsevier B.V. All rights reserved.Landslides present a geomorphological hazard in Alpine regions, threatening life, infrastructure and property. Here we present the development of a new regional landslide inventory (RI) for the European Alps. This database provides a substantial temporal and spatial picture of landsliding in the Alps, with particular focus on the Swiss and French Alps. We use segmented models to evaluate recording bias in the temporal record. We use scaling relationships to calculate landslide area based on a given volume for similar types of landslide; with the result of this being that 9.5% of the landslides recorded in the RI now have area data recorded. These landslide area data are then used to examine the log-linear trend, which exists between landslide area and frequency in inventories. We show that this relationship is present for this historical dataset; however, none of the individual databases, nor a unification of these, contain a complete record with the small and larger landslides being recorded more consistently. The use of segmented models on the temporal distribution of landslides in the RI shows that the post-1970 portion of the database is more reliable, highlighted through an improved power-law relationship, although the frequency of medium sized landslides is still underestimated. We show that creating a unified database (RI) can increase the reliability of datasets and consistency in recording for the use by researchers for attribution and detection studies.Lloyds of Londo

Database System Acceleration on FPGAs

Relational database systems provide various services and applications with an efficient means for storing, processing, and retrieving their data. The performance of these systems has a direct impact on the quality of service of the applications that rely on them. Therefore, it is crucial that database systems are able to adapt and grow in tandem with the demands of these applications, ensuring that their performance scales accordingly. In the past, Moore's law and algorithmic advancements have been sufficient to meet these demands. However, with the slowdown of Moore's law, researchers have begun exploring alternative methods, such as application-specific technologies, to satisfy the more challenging performance requirements. One such technology is field-programmable gate arrays (FPGAs), which provide ideal platforms for developing and running custom architectures for accelerating database systems. The goal of this thesis is to develop a domain-specific architecture that can enhance the performance of in-memory database systems when executing analytical queries. Our research is guided by a combination of academic and industrial requirements that seek to strike a balance between generality and performance. The former ensures that our platform can be used to process a diverse range of workloads, while the latter makes it an attractive solution for high-performance use cases. Throughout this thesis, we present the development of a system-on-chip for database system acceleration that meets our requirements. The resulting architecture, called CbMSMK, is capable of processing the projection, sort, aggregation, and equi-join database operators and can also run some complex TPC-H queries. CbMSMK employs a shared sort-merge pipeline for executing all these operators, which results in an efficient use of FPGA resources. This approach enables the instantiation of multiple acceleration cores on the FPGA, allowing it to serve multiple clients simultaneously. CbMSMK can process both arbitrarily deep and wide tables efficiently. The former is achieved through the use of the sort-merge algorithm which utilizes the FPGA RAM for buffering intermediate sort results. The latter is achieved through the use of KeRRaS, a novel variant of the forward radix sort algorithm introduced in this thesis. KeRRaS allows CbMSMK to process a table a few columns at a time, incrementally generating the final result through multiple iterations. Given that acceleration is a key objective of our work, CbMSMK benefits from many performance optimizations. For instance, multi-way merging is employed to reduce the number of merge passes required for the execution of the sort-merge algorithm, thus improving the performance of all our pipeline-breaking operators. Another example is our in-depth analysis of early aggregation, which led to the development of a novel cache-based algorithm that significantly enhances aggregation performance. Our experiments demonstrate that CbMSMK performs on average 5 times faster than the state-of-the-art CPU-based database management system MonetDB.:I Database Systems & FPGAs 1 INTRODUCTION 1.1 Databases & the Importance of Performance 1.2 Accelerators & FPGAs 1.3 Requirements 1.4 Outline & Summary of Contributions 2 BACKGROUND ON DATABASE SYSTEMS 2.1 Databases 2.1.1 Storage Model 2.1.2 Storage Medium 2.2 Database Operators 2.2.1 Projection 2.2.2 Filter 2.2.3 Sort 2.2.4 Aggregation 2.2.5 Join 2.2.6 Operator Classification 2.3 Database Queries 2.4 Impact of Acceleration 3 BACKGROUND ON FPGAS 3.1 FPGA 3.1.1 Logic Element 3.1.2 Block RAM (BRAM) 3.1.3 Digital Signal Processor (DSP) 3.1.4 IO Element 3.1.5 Programmable Interconnect 3.2 FPGADesignFlow 3.2.1 Specifications 3.2.2 RTL Description 3.2.3 Verification 3.2.4 Synthesis, Mapping, Placement, and Routing 3.2.5 TimingAnalysis 3.2.6 Bitstream Generation and FPGA Programming 3.3 Implementation Quality Metrics 3.4 FPGA Cards 3.5 Benefits of Using FPGAs 3.6 Challenges of Using FPGAs 4 RELATED WORK 4.1 Summary of Related Work 4.2 Platform Type 4.2.1 Accelerator Card 4.2.2 Coprocessor 4.2.3 Smart Storage 4.2.4 Network Processor 4.3 Implementation 4.3.1 Loop-based implementation 4.3.2 Sort-based Implementation 4.3.3 Hash-based Implementation 4.3.4 Mixed Implementation 4.4 A Note on Quantitative Performance Comparisons II Cache-Based Morphing Sort-Merge with KeRRaS (CbMSMK) 5 OBJECTIVES AND ARCHITECTURE OVERVIEW 5.1 From Requirements to Objectives 5.2 Architecture Overview 5.3 Outlineof Part II 6 COMPARATIVE ANALYSIS OF OPENCL AND RTL FOR SORT-MERGE PRIMITIVES ON FPGAS 6.1 Programming FPGAs 6.2 RelatedWork 6.3 Architecture 6.3.1 Global Architecture 6.3.2 Sorter Architecture 6.3.3 Merger Architecture 6.3.4 Scalability and Resource Adaptability 6.4 Experiments 6.4.1 OpenCL Sort-Merge Implementation 6.4.2 RTLSorters 6.4.3 RTLMergers 6.4.4 Hybrid OpenCL-RTL Sort-Merge Implementation 6.5 Summary & Discussion 7 RESOURCE-EFFICIENT ACCELERATION OF PIPELINE-BREAKING DATABASE OPERATORS ON FPGAS 7.1 The Case for Resource Efficiency 7.2 Related Work 7.3 Architecture 7.3.1 Sorters 7.3.2 Sort-Network 7.3.3 X:Y Mergers 7.3.4 Merge-Network 7.3.5 Join Materialiser (JoinMat) 7.4 Experiments 7.4.1 Experimental Setup 7.4.2 Implementation Description & Tuning 7.4.3 Sort Benchmarks 7.4.4 Aggregation Benchmarks 7.4.5 Join Benchmarks 7. Summary 8 KERRAS: COLUMN-ORIENTED WIDE TABLE PROCESSING ON FPGAS 8.1 The Scope of Database System Accelerators 8.2 Related Work 8.3 Key-Reduce Radix Sort(KeRRaS) 8.3.1 Time Complexity 8.3.2 Space Complexity (Memory Utilization) 8.3.3 Discussion and Optimizations 8.4 Architecture 8.4.1 MSM 8.4.2 MSMK: Extending MSM with KeRRaS 8.4.3 Payload, Aggregation and Join Processing 8.4.4 Limitations 8.5 Experiments 8.5.1 Experimental Setup 8.5.2 Datasets 8.5.3 MSMK vs. MSM 8.5.4 Payload-Less Benchmarks 8.5.5 Payload-Based Benchmarks 8.5.6 Flexibility 8.6 Summary 9 A STUDY OF EARLY AGGREGATION IN DATABASE QUERY PROCESSING ON FPGAS 9.1 Early Aggregation 9.2 Background & Related Work 9.2.1 Sort-Based Early Aggregation 9.2.2 Cache-Based Early Aggregation 9.3 Simulations 9.3.1 Datasets 9.3.2 Metrics 9.3.3 Sort-Based Versus Cache-Based Early Aggregation 9.3.4 Comparison of Set-Associative Caches 9.3.5 Comparison of Cache Structures 9.3.6 Comparison of Replacement Policies 9.3.7 Cache Selection Methodology 9.4 Cache System Architecture 9.4.1 Window Aggregator 9.4.2 Compressor & Hasher 9.4.3 Collision Detector 9.4.4 Collision Resolver 9.4.5 Cache 9.5 Experiments 9.5.1 Experimental Setup 9.5.2 Resource Utilization and Parameter Tuning 9.5.3 Datasets 9.5.4 Benchmarks on Synthetic Data 9.5.5 Benchmarks on Real Data 9.6 Summary 10 THE FULL PICTURE 10.1 System Architecture 10.2 Benchmarks 10.3 Meeting the Objectives III Conclusion 11 SUMMARY AND OUTLOOK ON FUTURE RESEARCH 11.1 Summary 11.2 Future Work BIBLIOGRAPHY LIST OF FIGURES LIST OF TABLE

Images of Immigrants and Refugees in Western Europe

"The topic of migration has become particularly contentious in national and international debates. Media have a discernable impact on overall societal attitudes towards this phenomenon. Polls show time and again that immigration is one of the most important issues occupying people’s minds. This book examines the dynamic interplay between media representations of migrants and refugees on the one hand and the governmental and societal (re)actions to these on the other. Largely focusing on Belgium and Sweden, this collection of interdisciplinary research essays attempts to unravel the determinants of people’s preferences regarding migration policy, expectations towards newcomers, and economic, humanitarian and cultural concerns about immigration’s effect on the majority population’s life. Whilst migrants and refugees remain voiceless and highly underrepresented in the legacy media, this volume allows their voices to be heard. Contributors: Leen d’Haenens (KU Leuven), Willem Joris (KU Leuven), Paul Puschmann (KU Leuven/Radboud University Nijmegen), Ebba Sundin (Halmstad University), David De Coninck (KU Leuven), Rozane De Cock (KU Leuven), Valériane Mistiaen (Université libre de Bruxelles), Lutgard Lams (KU Leuven), Stefan Mertens (KU Leuven), Olivier Standaert (UC Louvain), Hanne Vandenberghe (KU Leuven), Koen Matthijs (KU Leuven), Kevin Smets (Vrije Universiteit Brussel), Jacinthe Mazzocchetti (UC Louvain), Lorraine Gerstmans (UC Louvain), Lien Mostmans (Vrije Universiteit Brussel), and François Heinderyckx (Université libre de Bruxelles)

Patient-perceived health-related quality of life during recovery after total hip arthroplasty – a 6-month follow-up study

Potilaiden käsitys terveyteen liittyvästä elämänlaadusta lonkan tekonivelleikkauksen jälkeisenä toipumisaikana – kuuden kuukauden seurantatutkimus Tässä kaksivaiheisessa seurantatutkimuksessa tarkasteltiin potilaiden käsitystä terveyteen liittyvästä elämänlaadusta lonkan tekonivelleikkauksen jälkeisenä toipumisaikana. Tutkimuksen ensimmäisessä vaiheessa tarkoituksena oli sekä kuvailla potilaiden kokemuksia potilaana olosta, saamastaan hoidosta ja terveyspalveluorganisaatiosta että analysoida aikaisempien tutkimusten perusteella leikkauksen tuloksia potilaan kannalta. Toisessa vaiheessa tarkoituksena oli arvioida potilaiden kokemaa elämänlaatua leikkauksen jälkeen, ja sitä vaikuttivatko primaaritulokset (fyysinen toimintakyky, kipu, ahdistus) tai taloudelliset seuraukset (potilaiden itsensämaksamat kustannukset, palvelujen käyttö) terveyteen liittyvään elämänlaatuun. Tutkimuksen tavoitteena oli löytää mahdolliset kriittiset ajankohdat tai tekijät, jotka saattavat hidastaa toipumista ja siten huonontaa potilaiden elämänlaatua. Tätä tietoa voidaan käyttää hoitotyössä kun suunnitellaan sopivaa hoitoa ja tukea toipumisajalle. Tutkimuksen ensimmäisessä vaiheessa primaarileikkaukseen tulevat potilaat (n = 17) kuvailivat teemahaastatteluissa kokemuksiaan kahdesti leikkauksen jälkeen. Haastatteluaineisto analysoitiin induktiivisella sisällönanalyysilla. Lisäksi 17 tutkimusartikkelista analysoitiin deduktiivisella sisällönanalyysilla leikkauksen tuloksia potilaalle, tuloksiin vaikuttavia tekijöitä ja käytetyt tutkimusmetodit. Toisessa vaiheessa primaari- tai revisioleikkaukseen tulevat potilaat (n = 100) arvioivat leikkauksen tuloksia kuuden kuukauden ajan leikkauksen jälkeen: terveyteen liittyvää elämänlaatua, primaarituloksia ja taloudellisia seurauksia. Aineisto kerättiin erilaisilla mittareilla: Sickness Impact Profile, Finnish Version, Stait-Trait Anxiety Inventory, ja Numeric Rating Scale. Lisäksi käytettiin tätä tutkimusta varten tehtyjä kyselylomakkeita: Fyysinen toimintakyky-mittari, Palvelujen käyttö-mittari ja Kustannusmittari. Tutkimuksen toiseen vaiheen tulokset analysoitiin tilastollisilla menetelmillä. Potilaiden terveyteen liittyvä elämänlaatu parani ja kipu lievittyi leikkauksen jälkeen ja fyysinen toimintakyky lisääntyi toipumisaikana. Positiivisista muutoksista huolimatta potilaat kokivat ahdistusta samassa määrin kuin ennen leikkaustakin. Palvelujen käyttö vaihteli toipumisajan kuluessa ja potilaiden maksamissa kustannuksissa oli suuria vaihteluita. Fyysisen toimintakyvyn lisääntyminen ja kivun lieveneminen paransivat terveyteen liittyvää elämänlaatua. Sen sijaan huonompi elämänlaatu toipumisaikana oli yhteydessä suurempaan palvelujen käyttöön, kun taas kustannuksilla ei ollut yhteyttä elämänlaatuun. Potilaiden ominaispiirteet tulisi ottaa enemmän huomioon suunniteltaessa sopivaa leikkauksenjälkeistä hoitoa ja tukea. Potilaat tarvitsevat yksilöllisiä ohjeita, sillä monet taustatekijät (esim. ikä, sukupuoli, preoperatiivinen kipu, siviilisääty, ja leikkaustyyppi) vaikuttavat toipumiseen.This two-phase longitudinal follow-up study was conducted to examine the patientperceived impact of total hip arthroplasty when it is measured as changes in patients’ health-related quality of life. In descriptive phase I, the aim was twofold: first, to describe patients’ experiences of being a patient, of care, and of the health care organisation, and, second to describe patient outcomes of total hip arthroplasty on the basis of previous research. In explorative phase II the aim was to evaluate patientperceived health-related quality of life after surgery, and to what extent it is influenced by primary (physical function, pain, state anxiety) or economic (out-of-pocket-costs, service use) outcomes of total hip arthroplasty. The ultimate goal was to identify possible critical points of time as well as factors that may delay recovery and in that way worsen patients’ health-related quality of life. This knowledge may have uses innursing when planning postoperative patient care and support In phase I of the study 17 patients undergoing primary hip arthroplasty described their experiences in focused interviews twice after surgery. Inductive content analysis was used to analyse this data set. In addition, previous research papers (n = 17) were analysed using deductive content analysis to find out patient outcomes of THA, factors related to patient outcomes, and the research methods used. In phase II patients (n = 100) undergoing primary or revision hip arthroplasty evaluated the outcomes up to six months after surgery: health-related quality of life, primary, and economic outcomes. The data were collected by means of the Sickness Impact Profile, Finnish Version, Stait-Trait Anxiety Inventory, Numeric Rating Scale, and a purpose-designed Physical function questionnaire, Service use questionnaire and Out-of-pocket costs diary. The phase II data were analysed using statistical methods. Patients’ health-related quality of life was improved and pain relieved after surgery, and their physical function increased during recovery. Despite positive changes patients’ anxiety remained at the preoperative level. Service use varied with recovery and patients’ out-of-pocket costs showed wide variation. Improvements in physical function and relief from pain improved patients’ health- related quality of life, whereas a worse postoperative health-related quality was associated with increased service use but not with out-of-pocket costs. Patients’ individual characteristics should be taken more into consideration in nursing when planning postoperative, relevant and sufficient patient care for recovery and support, as patients need personally tailored short- and long-term advice, depending on several background factors (e.g. age, gender, preoperative pain, civil status, and type of surgery).Siirretty Doriast

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours

Concepção e realização de um framework para sistemas embarcados baseados em FPGA aplicado a um classificador Floresta de Caminhos Ótimos

Orientadores: Eurípedes Guilherme de Oliveira Nóbrega, Isabelle Fantoni-Coichot, Vincent FrémontTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica, Université de Technologie de CompiègneResumo: Muitas aplicações modernas dependem de métodos de Inteligência Artificial, tais como classificação automática. Entretanto, o alto custo computacional associado a essas técnicas limita seu uso em plataformas embarcadas com recursos restritos. Grandes quantidades de dados podem superar o poder computacional disponível em tais ambientes, o que torna o processo de projetá-los uma tarefa desafiadora. As condutas de processamento mais comuns usam muitas funções de custo computacional elevadas, o que traz a necessidade de combinar alta capacidade computacional com eficiência energética. Uma possível estratégia para superar essas limitações e prover poder computacional suficiente aliado ao baixo consumo de energia é o uso de hardware especializado como, por exemplo, FPGA. Esta classe de dispositivos é amplamente conhecida por sua boa relação desempenho/consumo, sendo uma alternativa interessante para a construção de sistemas embarcados eficazes e eficientes. Esta tese propõe um framework baseado em FPGA para a aceleração de desempenho de um algoritmo de classificação a ser implementado em um sistema embarcado. A aceleração do desempenho foi atingida usando o esquema de paralelização SIMD, aproveitando as características de paralelismo de grão fino dos FPGA. O sistema proposto foi implementado e testado em hardware FPGA real. Para a validação da arquitetura, um classificador baseado em Teoria dos Grafos, o OPF, foi avaliado em uma proposta de aplicação e posteriormente implementado na arquitetura proposta. O estudo do OPF levou à proposição de um novo algoritmo de aprendizagem para o mesmo, usando conceitos de Computação Evolutiva, visando a redução do tempo de processamento de classificação, que, combinada à implementação em hardware, oferece uma aceleração de desempenho suficiente para ser aplicada em uma variedade de sistemas embarcadosAbstract: Many modern applications rely on Artificial Intelligence methods such as automatic classification. However, the computational cost associated with these techniques limit their use in resource constrained embedded platforms. A high amount of data may overcome the computational power available in such embedded environments while turning the process of designing them a challenging task. Common processing pipelines use many high computational cost functions, which brings the necessity of combining high computational capacity with energy efficiency. One of the strategies to overcome this limitation and provide sufficient computational power allied with low energy consumption is the use of specialized hardware such as FPGA. This class of devices is widely known for their performance to consumption ratio, being an interesting alternative to building capable embedded systems. This thesis proposes an FPGA-based framework for performance acceleration of a classification algorithm to be implemented in an embedded system. Acceleration is achieved using SIMD-based parallelization scheme, taking advantage of FPGA characteristics of fine-grain parallelism. The proposed system is implemented and tested in actual FPGA hardware. For the architecture validation, a graph-based classifier, the OPF, is evaluated in an application proposition and afterward applied to the proposed architecture. The OPF study led to a proposition of a new learning algorithm using evolutionary computation concepts, aiming at classification processing time reduction, which combined to the hardware implementation offers sufficient performance acceleration to be applied in a variety of embedded systemsDoutoradoMecanica dos Sólidos e Projeto MecanicoDoutor em Engenharia Mecânica3077/2013-09CAPE

Mapping Digital Media: Hungary

Examines trends in media consumption; digital media's effects on public service broadcasters, journalism, and civic activism; trends in digital technology and business; and new media regulations' impact on freedom of expression. Makes recommendations