Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Microwave Active Filter Design

A simplified method for the project and design of microwave active filters is presented here. The presented design is based on the use of an active inductor that emulates an inductor behavior by implementing a passive variable phase- and amplitude-compensating network and amplifiers, forming a gyrator-C architecture. This method can be applied with success for the design of bandpass filters with very high performances in terms of integration and application from a few hundreds of MHz to tens of GHs with filter high dynamic range and frequency tuning capability

Mixed-mode impedance and reflection coefficient of two-port devices

From the point of view of mixed-mode scattering parameters, Smm, a two-port device can be excited using different driving conditions. Each condition leads to a particular set of input reflection and input impedance coefficient definitions that should be carefully applied depending on the type of excitation and symmetry of the two-port device. Therefore, the aim of this paper is to explain the general analytic procedure for the evaluation of such reflection and impedance coefficients in terms of mixed-mode scattering parameters. Moreover, the driving of a two-port device as a one-port device is explained as a particular case of a two-port mixed-mode excitation using a given set of mixed-mode loads. The theory is applied to the evaluation of the quality factor, Q, of symmetrical and non- symmetrical inductors.Ministerio de Innovación y Ciencia TEC2010-14825/MIC, TEC2010-21484Junta de Andalucía TIC-253

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

A 60nm CMOS, 3rd and 5th Order Low Pass Filter with Higher Cut-off Frequency

The design of CMOS based low pass filter for analog-to-digital, digital-to-analog and audio applications is described in this paper. Active load resistor and floating inductor is used for the implementation of low pass filter. CMOS technology has become dominant over bipolar technology for analog circuits design in mixed signal system. The differential floating active inductor is designed with CMOS and current sources. The floating inductor may be electronically tuned by varying external bias voltage as well as current. The simulations are obtained by using 65nm CMOS technology on Tanner EDA tool 13.0. The filters are synthesized from 3rd and 5th order low-pass LC prototype and designed using ladder structure. Keywords: Complementary Metal Oxide Semiconductor (CMOS), low pass filter (LPF), active resistor, Power delay product (PDP)

Novel active function blocks and their applications in frequency filters and quadrature oscillators

Kmitočtové filtry a sinusoidní oscilátory jsou lineární elektronické obvody, které jsou používány v široké oblasti elektroniky a jsou základními stavebními bloky v analogovém zpracování signálu. V poslední dekádě pro tento účel bylo prezentováno velké množství stavebních funkčních bloků. V letech 2000 a 2006 na Ústavu telekomunikací, VUT v Brně byly definovány univerzální proudový konvejor (UCC) a univerzální napět'ový konvejor (UVC) a vyrobeny ve spolupráci s firmou AMI Semiconductor Czech, Ltd. Ovšem, stále existuje požadavek na vývoj nových aktivních prvků, které nabízejí nové výhody. Hlavní přínos práce proto spočívá v definici dalších původních aktivních stavebních bloků jako jsou differential-input buffered and transconductance amplifier (DBTA), current follower transconductance amplifier (CFTA), z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), generalized current follower differential input transconductance amplifier (GCFDITA), voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), a minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Pomocí navržených aktivních stavebních bloků byly prezentovány původní zapojení fázovacích článků prvního řádu, univerzální filtry druhého řádu, ekvivalenty obvodu typu KHN, inverzní filtry, aktivní simulátory uzemněného induktoru a kvadraturní sinusoidní oscilátory pracující v proudovém, napět'ovém a smíšeném módu. Chování navržených obvodů byla ověřena simulací v prostředí SPICE a ve vybraných případech experimentálním měřením.Frequency filters and sinusoidal oscillators are linear electric circuits that are used in wide area of electronics and also are the basic building blocks in analogue signal processing. In the last decade, huge number of active building blocks (ABBs) were presented for this purpose. In 2000 and 2006, the universal current conveyor (UCC) and the universal voltage conveyor (UVC), respectively, were designed at the Department of Telecommunication, BUT, Brno, and produced in cooperation with AMI Semiconductor Czech, Ltd. There is still the need to develop new active elements that offer new advantages. The main contribution of this thesis is, therefore, the definition of other novel ABBs such as the differential-input buffered and transconductance amplifier (DBTA), the current follower transconductance amplifier (CFTA), the z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), the generalized current follower differential input transconductance amplifier (GCFDITA), the voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), and the minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Using the proposed ABBs, novel structures of first-order all-pass filters, second-order universal filters, KHN-equivalent circuits, inverse filters, active grounded inductance simulators, and quadrature sinusoidal oscillators working in the current-, voltage-, or mixed-mode are presented. The behavior of the proposed circuits has been verified by SPICE simulations and in selected cases also by experimental measurements.

Analysis of the high frequency substrate noise effects on LC-VCOs

La integració de transceptors per comunicacions de radiofreqüència en CMOS pot quedar seriosament limitada per la interacció entre els seus blocs, arribant a desaconsellar la utilització de un únic dau de silici. El soroll d’alta freqüència generat per certs blocs, com l’amplificador de potencia, pot viatjar pel substrat i amenaçar el correcte funcionament de l’oscil·lador local. Trobem tres raons importants que mostren aquest risc d’interacció entre blocs i que justifiquen la necessitat d’un estudi profund per minimitzar-lo. Les característiques del substrat fan que el soroll d’alta freqüència es propagui m’és fàcilment que el de baixa freqüència. Per altra banda, les estructures de protecció perden eficiència a mesura que la freqüència augmenta. Finalment, el soroll d’alta freqüència que arriba a l’oscil·lador degrada al seu correcte comportament. El propòsit d’aquesta tesis és analitzar en profunditat la interacció entre el soroll d’alta freqüència que es propaga pel substrat i l’oscil·lador amb l’objectiu de poder predir, mitjançant un model, l’efecte que aquest soroll pot tenir sobre el correcte funcionament de l’oscil·lador. Es volen proporcionar diverses guies i normes a seguir que permeti als dissenyadors augmentar la robustesa dels oscil·ladors al soroll d’alta freqüència que viatja pel substrat. La investigació de l’efecte del soroll de substrat en oscil·ladors s’ha iniciat des d’un punt de vista empíric, per una banda, analitzant la propagació de senyals a través del substrat i avaluant l’eficiència d’estructures per bloquejar aquesta propagació, i per altra, determinant l’efecte d’un to present en el substrat en un oscil·lador. Aquesta investigació ha mostrat que la injecció d’un to d’alta freqüència en el substrat es pot propagar fins arribar a l’oscil·lador i que, a causa del ’pulling’ de freqüència, pot modular en freqüència la sortida de l’oscil·lador. A partir dels resultats de l’anàlisi empíric s’ha aportat un model matemàtic que permet predir l’efecte del soroll en l’oscil·lador. Aquest model té el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem. el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem.The integration of transceivers for RF communication in CMOS can be seriously limited by the interaction between their blocks, even advising against using a single silicon die. The high frequency noise generated by some of the blocks, like the power amplifier, can travel through the substrate, reaching the local oscillator and threatening its correct performance. Three important reasons can be stated that show the risk of the single die integration. Noise propagation is easier the higher the frequency. Moreover, the protection structures lose efficiency as the noise frequency increases. Finally, the high frequency noise that reaches the local oscillator degrades its performance. The purpose of this thesis is to deeply analyze the interaction between the high frequency substrate noise and the oscillator with the objective of being able to predict, thanks to a model, the effect that this noise may have over the correct behavior of the oscillator. We want to provide some guidelines to the designers to allow them to increase the robustness of the oscillator to high frequency substrate noise. The investigation of the effect of the high frequency substrate noise on oscillators has started from an empirical point of view, on one hand, analyzing the noise propagation through the substrate and evaluating the efficiency of some structures to block this propagation, and on the other hand, determining the effect on an oscillator of a high frequency noise tone present in the substrate. This investigation has shown that the injection of a high frequency tone in the substrate can reach the oscillator and, due to a frequency pulling effect, it can modulate in frequency the output of the oscillator. Based on the results obtained during the empirical analysis, a mathematical model to predict the effect of the substrate noise on the oscillator has been provided. The main advantage of this model is the fact that it is based on physical parameters of the oscillator and of the noise, allowing to determine the measures that a designer can take to increase the robustness of the oscillator as well as the consequences (trade-offs) that these measures have over its global performance. This model has been compared against both, simulations and real measurements, showing a very high accuracy to predict the effect of the high frequency substrate noise. The usefulness of the presented model as a design tool has been demonstrated in two case studies. Firstly, the conclusions obtained from the model have been applied in the design of an ultra low power consumption 2.5 GHz oscillator robust to the high frequency substrate noise with characteristics which make it compatible with the main communication standards in this frequency band. Finally, the model has been used as an analysis tool to evaluate the cause of the differences, in terms of performance degradation due to substrate noise, measured in two 60 GHz oscillators with two different tank inductor shielding strategies, floating and grounded. The model has determined that the robustness differences are caused by the improvement in the tank quality factor and in the oscillation amplitude and no by an increased isolation between the tank and the substrate. The model has shown to be valid and very accurate even in these extreme frequency range.Postprint (published version

High Performance Tunable Active Inductors For Microwave Circuits

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2016Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2016RF uygulamalarında enduktif karakteristiğe önemli ölçüde ihtiyaç duyulmaktadır; bunlar, özellikle filtreler, düşük gürültülü yükselteçler (LNA, low noise amplifiers), gerilim kontrollü osilatörler (VCO, voltage controlled oscillators), pek çok farklı türde yükselteç için band genişliği iyileştirilmesi, faz kaydırıcılar, güç bölücüler ve eşleştirme (matching) devreleri vb. uygulamalardır. Pasif sarmal çip-içi CMOS endüktansların eksik yönleri ayrıntılı olarak literatürde tartışılmıştır. Bu tür endüktanslar düşük değer katsayısı (quality factor), düşük öz-rezonans frekansı (SRF, self-resonance frequency), sabit ve düşük değerli endüktans ve geniş bir silikon (silicon) alanı gerektirmeleri gibi istenmeyen özelliklere sahiptirler. Diğer yandan, MOS transistorlar kullanılarak sentezlenen CMOS aktif endüktansların, pasif sarmal eşdeğer yapıları ile karşılaştırıldığında pek çok çekici karakteristik özellik sunabildikleri gösterilmiştir. Bunlar; geniş bir bölgede ayarlanabilir öz-rezonans frekansı başarımı, geniş bir bölgede ayarlanabilir endüktans başarımı, geniş bir bölgede ayarlanabilir değer katsayısı başarımı, CMOS teknolojileri ile tümüyle gerçeklenebilme ve az alan kaplama gibi karakteristik özellikleri olarak ortaya konulmaktadır. Literatürde jiratör-C (GC) prensibi, topolojisi, karakterizasyonu ve uygulamaları ayrıntılı olarak ele alınmaktadır. İşlemsel geçiş-iletkenliği kuvvetlendiricisi (OTA, operational transconductance amplifier) ile gerçeklenen GC devreleri, RF uygulamaları için oldukça uygundur. Bu özellik, GC yapılarının söz konusu yapı kullanılarak en az sayıda aktif eleman ile gerçeklenebilmesinden kaynaklanmaktadır. Gerek topraklı (grounded) gerekse yüzen (floating) aktif endüktansların GC devreleri ile gerçeklenebildiği gösterilmiştir. Aktif endüktansların başarımlarının nicel olarak ölçülmesi amacıyla, çok sayıda ölçüt ortaya konulmuştur. Bu ölçütler frekans çalışma aralığı, endüktans ayarlanabilirliği, değer katsayısı, gürültü ve güç tüketimi gibi temel özellikleri içerirler. CMOS transistorların parazitik bileşenlerinden dolayı tasarlanan aktif endüktanslar belirli bir frekans bölgesinde endüktif davranış gösterirler. Alt frekans sınırı, GC devrelerinin sıfır frekansı ile belirlenirken; üst frekans sınırı ise öz-rezonans frekansı ile belirlenir. Aktif endüktansların pasif sarmal eşdeğer yapılarına göre en önemli üstünlüklerinden biri de; endüktanslarının geniş bir değer aralığıunda ayarlanabilir olmasıdır. GC aktif endüktansların endüktans değeri, transistorların geçiş-iletkenliklerinin ya da MOS varaktörlerle gerçeklenen yük kapasitanslarının değiştirilmesi ile ayarlanabilir. Literatürde, GC topolojisine dayalı pek çok CMOS AI (active inductor) devresi bildirilmiştir. Bunların tümü, farklı teknikler kullanılarak yüksek başarımlı AI yapıları oluşturmayı amaçlamışlardır. Bu tezde, bunlardan güncel olan bazı GAI (grounded AI) ve FAI (floating AI) yapıları gözden geçirilmiştir. Bunlardan bazıları, değer katsayısını (QF) iyileştirmek amacıyla, AI kaybını telafi etmek için negatif direnç kullanmışlardır. GC yapıları RF uygulamaları için tasarlandıklarında en az sayıda transistor kullanımı çok kritiktir. Çünkü bu durum AI öz-rezonans frekansının artmasına yardımcı olur. AI’ler, kazanç artırma amacıyla LNA’lerde geniş kullanım alanı bulabilmektedirler. Diğer taraftan, AI yapılarının en önemli dezvantajlarından biri gürültü başarımının pasif endüktanslara nispeten yüksek olmasıdır. Literatürde bu dezavantajı gidermek amacıyla teklif edilen yaklaşımlardan biri dejenerasyon direncinin bulunduğu bir geribesleme katı kullanılarak girişe gelen gürültü katkısını azaltmayı amaçlamıştır. Literatürde teklif edilen tekniklerin amacı, parazitik bileşenlerin etkisini azaltmak ya da tümüyle ortadan kaldırmaktır. Bu tezde, ileri devre teknikleri kullanılarak, yeni topraklı (grounded) ve yüzen (floting) AI yapıları tasarlanmıştır. AI giriş ve çıkış düğümlerine ait iletkenlikleri azaltmak için çoklu-düzenlenmiş kaskod (multi-regulated cascode, MRC) katları QF değerini iyileştirme amacıyla kullanılmaktadır. MRC katı PMOS transistorlarıyla oluşturulmuştur. PMOS transistor kullanımı, • ikinci kat kutuplamasını ayarlayabilmek amacıyla, giriş transistor boyutunun mümkün olduğunca azaltılmasını, • ana AC işaret yolundaki transistor sayısının azaltılmasını, sağlamaktadır. Tezde sunulan teorik analiz ve serim sonrası benzetim sonuçları, MRC katı kullanımının AI özelliklerine yaptığı etkiyi göstermektedir. Elde edilen sonuçlar bu katların AI tasarımında yüksek QF elde edilmesini imkan tanıdığını ortaya koynaktadır. Literatürde, iki ana AI başarım karakteristiği olan SRF ve QF başarımlarının iyileştirmesi için çok sayıda çalışma bulunmaktadır. Bu tezde, birbirlerini etkilemeksizin SRF ve QF başarımlarının ayarlanabilmesi özelliğine sahip bir AI’ın tasarımı ve benzetgimi yapılmıştır. Kaskod ve RC geribesleme yapıları yeni AI tasarımında kullanılmıştır. Daha önce de tartışıldığı üzere, AI karakterizasyonu açısından giriş transistoru çok önemlidir. Girişi transistorunun kaskodlanması, ilk jiratörün geçiş-iletkenliğinin ve giriş parazitik kapasitansının birbirinden bağımsız olarak ayarlanması gibi önemli ve kullanışlı bir özelliği beraberinde getirir. Bunun yanısıra, endüktansın değeri diğer transistorun iletkenliği ile ayarlanabilir. AI parazitik seri-rezistansını yok etmek amacıyla kullanılan RC geribeslemesi, QF iyileştirmesini sağlayabilmektedir. Kaskod transistorların kutuplama koşulu bir diyot-bağlı transistor ile sağlandığından; önerilen yapı proses, gerilim ve sıcaklık değişimleri açısından kararlı ve yüksek başarımlıdır. AI yapılarında karşılaşılan düşük gürültü başarımı, AI’ların LNA gibi RF uygulamalarda kullanımını sınırlamaktadır. Bir AI’ın ana gürültü kaynağı giriş transistorudur. Düşük gürültülü AI elde etmek için, giriş transistoru yeterince büyük boyutlu olarak tasarlanmalıdır. Ne var ki, büyük boyutlu böyle bir transistor, düşük bir SRF ve dolayısıyla sınırlı bir endüktif bandı beraberinde getirir. Bu tezde, düşük gürültülü ve az kayıplı uygun bir AI, düşük gürültü gerektiren RF uygulamaları için sunulmuştur. Teklif edilen AI devresindeki tüm transistorların ortak-kaynak (common-source, CS) yapısında kullanılması, düşük iletkenliğe sahip düğümlerin dolayısıyla yüksek QF değerine sahip bir AI’ın elde edilmesine olanak sağlamaktadır. AI gürültüsünü azaltmak için, sırasıyla P-tipi MOS transistorlar ve ileri-besleme yolu yapısı (feed-forward path, FFP) kullanılmaktadır. Bilindiği gibi, sensörler çok çeşitli fiziksel büyüklüklerin eletrik mühendisiliği alanına taşınmasını sağlamaktadır. Çok geniş kullanım alanı bulan sensör tiplerinden biri kapasitif mikro algılıyıcılardır. Kapasitif mikro algılayıcılar mekanik hareketleri küçük kapasitans değişimlerine çevirirler. Micro algılayıcıdaki kapasitans değişimi femto-Farad mertebesinde olup algılamayı zorlaştırmaktadır. Diğer yandan, küçük bir kapasitans değişimini yüksek bir empedans değişimine çevirebilmeleri dolayısıyla, GC topolojilerinin kapasitif algılayıcılarda kullanılabileceğini söylemek mümkündür. Bu tezde, bu düşünceden yola çıkılarak, kesit duyarlılığını yok etme yeteneğine sahip yeni bir 3-eksen ivme-ölçer tasarlanmıştır. Yapının, her eksendeki ivmeyi bağımsız olarak algılayabilmesi için, algılayıcı elektrodları uygun olarak yerleştirilmiştir. Daha sonra, bir kapasitif algılayıcıdaki çok küçük kapasitans değişimlerini algılayabilmek için yeni bir GC yapısı teklif edilmiştir. Önerilen yapıda, çalışma frekansı aralığı ve ölçekleme çarpanı, kutuplama akımlarının ayarlanması suretiyle birbirini etkilemeksizin ayarlanabilmektedir. Ayrıca, önerilen yapıda, parazitik bileşenlerin etkisini yok etmek için RC geribesleme ve kaskod yapılar kullanılmaktadır. Son olarak, bu tezde sunulan AI’ların çok amaçlı özellikte olduğunu göstermek amacıyla, 3 ve 6. dereceden geniş bantlı mikrodalga filtrelerde kullanılmaları ele alınmıştır. İlki 3. dereceden bir Chebyshev alçak geçiren filtredir. Basitleştirilmiş gerçel frekans tekniği (SRFT, simplified real frequency technique) ile tasarlanan ikincisi ise, 6. dereceden bir Chebyshev band geçiren filtredir. Filtrelerin benzetimle elde edilmiş frekans yanıtları, bu tezde sunulan AI’ların literatürdeki yapılara güçlü birer alternatif olduklarını ortaya koymaktadır.There is critical need for inductive characteristics in RF applications, especially in filters, LNA, VCO, bandwidth-enhancement in many kinds of amplifiers, phase shifters, power divider and matching networks. The drawbacks of using passive and spiral inductors in CMOS process are discussed in the literature. It is shown that these kind of inductors suffer from a low quality factor, a low self-resonant frequency, a low and fixed inductance value and the need for a large silicon area. Furthermore, it is shown in the literature that CMOS Active Inductors (AIs), which are synthesized using MOS transistors, offer a number of attractive characteristics as compared with their spiral counterparts. These characteristics include a low silicon consumption, a large and tunable self-resonant frequency, a large and tunable inductance, a large and tunable quality factor, and fully realizable in digital CMOS technologies. Then principles, topologies, characterizations and implementation of the Gyrator-C (GC) network is discussed in-depth. The GC networks, which are implemented by operational transconductance amplifier, are suitable for RF application. This property arises from their minimum usage of active elements. It is shown that both grounded and floating active inductors can be implemented by GC networks. To provide a quantitative measure of the performance of AIs, a number of figure-of-merits have been introduced in the thesis. These figure-of-merits include frequency range, inductance tunability, quality factor, noise and power consumption. Due to parasitic components of CMOS transistors, designed AIs have inductive behavior in a specified frequency range. The low frequency bound is set by the frequency of the zero of the gyrator-C networks while the upper frequency bound is set by Self-Resonance Frequency (SRF). One of the key advantages of active inductors over their spiral counterparts is the large tunability of their inductance. The inductance of GC AIs can be tuned by varying either the transconductances of the transconductors or the load capacitance, which is implemented by MOS varactor. Based on GC topology, there are many reported CMOS AI circuits in literature. All of them have tried to invent high performance AI by using different techniques. Some of recent proposed Grounded AI (GAI) and Floating AI (FAI) circuits are reviewed in the thesis. Some of them use negative resistor to compensate the loss of AI for QF enhancement. Some others try to use minimum number of transistors in order to increase the self-resonance frequency of AI for RF applications. In some applications, AIs are used in LNA circuits for gain boosting purpose. In that applications, designers have tried to cancel the noise of AI by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. The main aim of all the techniques is to cancel or reduce the effects of parasitic components. In the thesis, four new grounded and floating AIs are designed by using advanced circuit techniques. The first one, Multi Regulated Cascode (MRC) stages are employed for lowering conductance in input and output nodes of AI. Thus, Q performance is improved. Since these stages are used only for increasing impedance of input/output nodes, they are made up of PMOS transistors in order to: • minimize the input transistor as small as possible in order to adjust second stage biasing, • decrease the number of transistors in main path of AC signal Theoretical analysis and post-layout simulation results shows the effectiveness of using MRC stages usage in properties of AI. High Q symmetric floating version of low loss inductor is also designed by utilizing MRC stages. Designers do their best to improve SRF and QF, two main characteristics in term of AI performance. An AI with ability to adjust its SRF and QF without affecting each other is designed and simulated as a third. The cascoding and RC feedback structures are used in the new design of AI. As it discussed before, input transistor is very important regarding to AI characterizations. Cascoding input transistor gives the ability to adjust the first gyrator’s transconductance and input parasitic capacitance independently which it results in adjusting the self-resonance frequency and quality factor separately. Due to our best knowledge from literature reviewing, it is first time that the properties of an inductor can be adjusted independently. Furthermore, the inductance value can be adjusted by other transistor’s transconductances. Also, the RC feedback is utilized to cancel the parasitic series-resistance of AI which results in QF enhancement. Since, bias condition of cascoding transistors is provided by a diode-connected transistor, the proposed structure is robust in terms of performance over variation in process, voltage and temperature. The Noise of designed AIs has limited the use of them in RF applications such as LNAs. The main noise source of an AI is its input transistor. In order to have low noise AI, the input transistor should be designed large enough. But it leads to low SRF which limited the inductive frequency band. As a fourth active inductor design, a low-noise and low-loss AI is presented suitable for RF low noise applications. Utilizing all transistors in Common Sourse (CS) configuration on the AI circuit leads to low conductance nodes which causes the AI to have high Q. P-type MOS transistors and Feed-Forward Path (FFP) are employed to decrease noise of the AI, respectively. The GC topologies can convert a low capacitance variation to high impedance changing which makes it a good choice for capacitive sensors. The capacitive based micro sensors convert mechanical signals to small capacitance variation. The capacitance variation in micro sensor is in the range of femto-Farads which makes it difficult to sense. Thus, the GC topologies can be used in capacitive sensors in order to sense small capacitive variations. In the thesis, this technique is used in a new accelerometer sensor. It is first time that a gyrator-C network is employed as an interface circuit for capacitive change detection in micro sensors. The new accelerometer structure is designed by using with ability to cancel cross section sensitivity. The sensor’s electrodes are located in such a way that enables the structure to detect acceleration in 3-axis independently. Embedding all 3-axis detecting electrodes in a single proof mass and ability to detect acceleration orientation are salient features of the proposed sensor. Consequently, a new GC configuration for sensing very small capacitance changes in a capacitive sensor is presented in the thesis. In the proposed configuration, the operating frequency range and scaling factor can be adjusted without affecting each other by tuning the bias currents of utilized gyrators. In addition, the proposed configuration employs RC feedback together with the cascoding technique to cancel the effect of the parasitic components in order to get accurate scaling from gyrator-C network. Finally, in order to show versatility of designed AIs, they are used in designed third and sixth order broadband microwave filters. The first one is a third order Chebyshev low pass filter. The second one, which is designed by using simplified real frequency technique is a sixth order Chebyshev band pass filter. The simulated frequency response of filters prove the workability of the designed AIs.DoktoraPh