Nanowire Transistors and RF Circuits for Low-Power Applications

The background of this thesis is related to the steadily increasing demand of higher bandwidth and lower power consumption for transmitting data. The work aims at demonstrating how new types of structures, at the nanoscale, combined with what is referred to as exotic materials, can help benefit in electronics by lowering the consumed power, possibly by an order of magnitude, compared to the industry standard, silicon (Si), used today. Nanowires are semiconductor rods, with two dimensions at the nanoscale, which can be either grown with a bottom-up technique, or etched out with a top-down approach. The research interest concerning nanowires has gradually increasing for over two decades. Today, few have doubts that nanowires represent an attractive alternative, as scaling of planar structures has reached fundamental limits. With the enhanced electrostatics of a surrounding gate, nanowires offer the possibility of continued miniaturization, giving semiconductors a prolonged window of performance improvements. As a material choice, compound semiconductors with elements from group III and V (III-Vs), such as indium arsenide (InAs), have the possibility to dramatically decrease power consumption. The reason is the inherent electron transport properties of III-Vs, where an electron can travel, in the order of, 10 times faster than in Si. In the projected future, inclusion of III-Vs, as an extension to the Si-CMOS platform, seems almost inevitable, with many of the largest electronics manufacturing companies showing great interest. To investigate the technology potential, we have fabricated InAs nanowire metal-oxide-semiconductor field effect transistors (NW-FETs). The performance has been evaluated measuring both RF and DC characteristics. The best devices show a transconductance of 1.36 mS/µm (a device with a single nanowire, normalized to the nanowire circumference) and a maximum unilateral power gain at 57 GHz (for a device with several parallel nanowires), both values at a drive voltage of 0.5 V. The performance metrics are found to be limited by the capacitive load of the contact pads as well as the resistance in the non-gated segments of the nanowires. Using computer models, we have also been able to extract intrinsic transport properties, quantifying the velocity of charge carrier injection, which is the limiting property of semi-ballistic and ballistic devices. The value for our 45-nm-in-diameter nanowires, with 200 nm channel length, is determined to 1.7∙107 cm/s, comparable to other state-of-the-art devices at the same channel length. To demonstrate a higher level of functionality, we have connected several NW-FETs in a circuit. The fabricated circuit is a single balanced differential direct conversion mixer and is composed of three stages; transconductance, mixing, and transimpedance. The basic idea of the mixer circuit is that an information signal can either be extracted from or inserted into a carrier wave at a higher frequency than the information wave itself. It is the relative size of the first and the third stage that accounts for the circuit conversion gain. Measured circuits show a voltage conversion gain of 6 dB and a 3-dB bandwidth of 2 GHz. A conversion mixer is a vital component when building a transceiver, like those found in a cellphone and any other type of radio signal transmitting device. For all types of signals, noise imposes a fundamental limitation on the minimal, distinguishable amplitude. As transistors are scaled down, fewer carriers are involved in charge transport, and the impact of frequency dependent low-frequency noise gets relatively larger. Aiming towards low power applications, it is thus of importance to minimize the amount of transistor generated noise. Included in the thesis are studies of the level and origin of low-frequency 1/f-noise generated in NW-FETs. The measured noise spectral density is comparable to other non-planar devices, including those fabricated in Si. The data suggest that the level of generated noise can be substantially lowered by improving the high-k dielectric film quality and the channel interface. One significant discovery is that the part of the noise originating from the bulk nanowire, identified as mobility fluctuations, is comparably much lower than the measured noise level related to the nanowire surface. This result is promising as mobility fluctuations set the lower limit of what is achievable within a material system

Moving towards high carrier mobility power devices in silicon and silicon carbide

This thesis reports on recent progress regarding the characterization, design and fabrication of modern power semiconductor devices in Silicon (Si) as well as in the promising wide band gap material Silicon Carbide (SiC). Up to now, state of the art power devices are architectured on the basis of monocrystalline Si-wafers. This is due to the high material quality of Si in combination with the availability of a mature and reliable fabrication technology based on a well-established process library. However, more and more sophisticated device designs such as e.g. the Super-Junction (SJ) architecture require an increasing number of fabrication steps therefore increasing the amount of possible sources of error. Further, more complex three-dimensional dopant distribution profiles are needed for the devices to withstand the high blocking voltage demands of current power semiconductor applications when operated in reverse direction. This dopant distribution has to be monitored, at least for control samples, after implantation, after further thermal processes and during the duty cycle. To ensure reliable device operation, in particular for charge compensated devices, this monitoring or mapping has to be performed locally with high precision and sensitivity. In this work complementary Scanning Probe Microscopy (SPM) based methods like: Kelvin Probe Force Microscopy (KPFM), Scanning Capacitance Force Microscopy (SCFM) and Scanning Spreading Resistance Microscopy (SSRM) have been explored for a precise monitoring of carrier concentration profiles. This is due to the fact that so far none of the established industrial techniques such as e.g. Secondary Ion Mass Spectrometry (SIMS) or Spreading Resistance Probe (SRP) was mature enough to simultaneously full-fill all the major requirements of the semiconductor industry in terms of spatial resolution, sensitivity, reproducibility and the ability to quantify dopant concentrations. Further, SIMS is probing the chemical composition rather than the charge carrier distribution. To ‘look inside’ the inhomogeneously doped sample, smooth device cross-sections need to be prepared in a reliable manner and without distorting the ‘as implanted/activated’ dopant profile. In this way artefacts arising from a topographic signal can be ruled out. For Si the easiest way would be to cleave the wafer along a certain crystallographic direction. However, since the SPM methods presented here shall serve as a characterization tool with a general validity another approach that is also suitable for different crystal structures and materials with a hardness close to diamond had to be found. For this reason a chemical mechanical polishing (CMP) procedure had been developed at PSI. This process was optimized for maintaining a low surface state density as it is important to avoid a complete pinning of the Fermi level for the KPFM measurements. The subsequent Atomic Force Microscopy (AFM) imaging has been performed in collaboration with the experts in the research group of Prof. Ernst Meyer at the University of Basel. Within this project it has been demonstrated that every SPM derived method is capable to qualitatively map carrier concentrations down to an unprecedented low regime. However, a difference regarding the lateral resolution was observed which can be understood by different information depths depending on the underlying physical quantity to be measured together with an imperfect surface preparation which is leading to an accumulation or depletion of defects at the surface. The most critical technique in that sense - due to its high surface sensitivity - is the contact potential difference measurement that is utilized by KPFM to draw conclusions on the carrier concentration. By laser illumination of the sample during the KPFM experiment a Surface Photo Voltage (SPV) occurs in a surface near layer with a thickness in the order of the minority carrier diffusion length. Thus, the surface sensitivity is reduced and the signal distortion due to the unfavourable influence of surface defects gets less pronounced. Even though SCFM is also based on the detection of the electrostatic force that develops between the tip and the sample, this method is less affected by the surface because it is probing a different physical quantity, namely the total capacitance of the rather extended oxide/depletion layer capacitance system. Furthermore, the magnitude of the SCFM signal scales inverse proportionally with respect to the carrier concentration, hence this method is theoretically offering the highest sensitivity in the low concentration regime. Nevertheless, a quantification scheme for this technique is still in development and further work on locally acquired spectroscopic capacitance-voltage (C-V ) measurements is needed towards a reliable quantification procedure. The third SPM derived method SSRM, is operated in contact mode under high normal forces to ensure that the spreading resistance is the dominant resistance contribution for the current flowing between the tip and the sample. Under these circumstances the local carrier concentration and its impact on the magnitude and the sign of the output current can be investigated in a very accurate and quantitative manner. Beside that, the high mechanical forces cause an abrasive motion of the tip while scanning the sample. This feature is beneficial in two ways: on one hand the native oxide and the underlying defect-rich surface layer are removed while on the other hand a phase transformation of a tiny sample volume just below the tip occurs which locally decreases the resistivity and increases the spatial resolution. Hence, the SSRM technique is showing a high degree of reproducibility and is therefore ideal for quantitative studies. As mentioned above the considerable complexity of the fabrication process and the limited material properties of Si in terms of a high critical electric field and a high thermal conductivity accelerated the search for novel substrates for power semiconductor applications. Beside offering an order of magnitude higher critical electric field due to its wide band gap (WBG), SiC also attracted attention since it can be thermally oxidized resulting in a silicon dioxide (SiO2) layer as its native oxide. Therefore, this material has been classified as most promising and theoretical improvements of a - by a factor of 400 - lower ON-resistance have been calculated. However, to date SiC devices are facing other problems related to the engineering of dopant profiles and the more complex nature of the oxidation process which limit their performance and hinder their large-scale commercialization. The incorporation of a specific dopant distribution in SiC is most effectively done by an ion implantation process followed by a high temperature annealing step which is needed to restore the crystal structure after implantation-induced damage and to electronically activate the dopant atoms. This is caused by the fact that in SiC due to its wide band gap of 2.4-3.2 eV (depending on its poly-type) basically no dopant diffusion at reasonable thermal budgets occurs. Notably, not all of these dopant atoms are ionized and contribute to the electric conduction within the semiconductor. Especially the hole concentration p and the acceptor concentration NA can differ significantly in SiC due to the large ionization energies. Hence it has to be taken into account that the final performance of a SiC power device might be inferior to the expected performance from the implantation parameters. This behaviour is in clear contrast to Si where at room temperature basically all donor and acceptor atoms are ionized and no further differentiation between the dopant and the carrier (electronically active dopant) profile has to be made. The above mentioned SPM methods are sensitive to the carrier rather than to the dopant profile and within this work it has been demonstrated that e.g. the p-doped guard ring structure of a SiC Schottky diode which is shielding the metal contact from high electric fields that occur under reverse bias operation can be resolved. Another challenge for SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are low carrier mobilities inside the thin conducting channel at the semiconductor/oxide interface and threshold voltage instabilities. Due to the more complex nature of the oxidation process which requires the removal of carbon atoms in the form of CO or CO2 from the SiC crystal the SiC/SiO2 interface is showing a high density of interface trap states that act as scattering centres and degrade the carrier mobility. Hence, experimentally observed charge carrier mobilities are by a factor of 10 below the theoretical value of the bulk material. Thereby the ON-resistance which is inverse proportional to the mobility is increased which is leading to a higher amount of power dissipation in the ON-state of the device. Unsurprisingly, a lot of research effort has been triggered in this direction resulting in breakthrough called post-oxidation annealing (POA) under gaseous ambients. Nitrogen and phosphorous based chemistries have shown a passivating effect on the density of interface trap states. However, the origin of this mechanism is not yet fully understood. A possible explanation is a counter-doping effect within a thin layer at the semiconductor surface. A second - maybe easier - pathway to increase the channel mobility is the utilization of the crystal anisotropy. The mobility strongly depends on the orientation of the channel with respect to the crystallographic axis. Among them the 1120 direction exhibits the highest mobility. In the here presented project this approach has been utilized to improve the device performance without changing too many parameters regarding the oxidation or post-oxidation treatments at the same time. In this case the remaining challenge was to develop an etching process which is able to etch several um deep trenches into SiC and to precisely control the shape of the resulting trench profile. It has been demonstrated that sharp corners that would cause field crowding at the edges can be eliminated by the usage of very small DC biases applied between the electrode of the plasma chamber and the substrate. Furthermore, the steepness of the sidewalls could be controlled by the composition of the plasma gas flows. Contrary to previous reports we found that the addition of oxygen to the dry etching process is not helping to avoid microtrenching. Either a pure SF6 based process or an SF6 based process with the addition of Ar have shown the best results. With this success a full manufacturing cycle for a nanoscale trench MOSFET has been designed

ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS.

L’objectiu principal d’aquest treball és el desenvolupament d’un model compacte per a MOSFETs de múltiple porta d’escala nanomètrica, que sigui analític, basat en la física del dispositiu, i predictiu per a simulacions AC i DC. Els dispositius investigats són el MOSFET estàndar en mode d’inversió, a més d’un nou dispositiu anomenat “junctionless MOSFET” (MOSFET sense unions). El model es va desenvolupar en una formulació compacta amb l’ajuda de l’equació de Poisson i la tècnica de la transformación conforme de Schwarz-Cristoffel. Es varen obtenir les equacions del voltatge llindar i el pendent subllindar. Usant la funció W de Lambert, a més d’una funció de suavització per a la transcició entre les regions de depleció i acumulació, s’obté un model unificat de la densitat de càrrega, vàlid per a tots els modes d’operació del transistor. S’estudien també les dependències entre els paràmetres físics del dispositiu i el seu impacte en el seu rendiment. Es tenen en compteefectes importants de canal curt i de quantització. Es discuteixen també la simetria al voltant de Vds= 0 V, i la continuïtat del corrent de drenador en les derivades d’ordre superior. El model va ser validat mitjançant simulacions TCAD numèriques i mesures experimentals.El objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones). El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET. The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data

Ab initio scattering from random discrete charges and its impact on the intrinsic parameter fluctuations in nano-CMOS devices

This thesis is concerned with the Monte Carlo simulation of device parameter variation associated with the discrete nature and random variation of ionized impurity atoms within ultra-small conventional n-MOS devices. In particular, the Monte Carlo method is applied to accurately resolve electron interactions with individual ionized impurity atoms and in so doing capture the variation in impurity scattering associated with randomly configured dopant distributions. To date, variation in transport due to position dependent variation in Coulomb scattering has not received any attention although is expected to increase the inherent device parameter variation.A detailed methodology for the accurate treatment of Coulomb scattering within the Ensemble Monte Carlo framework is presented and verified. Improvement over existing methodologies is presented with a short-range force model that significantly reduces errors in conservation of energy during short-range attractive interactions compared with models proposed in similar work. Details of the simulated reproduction of bulk mobility are thoroughly presented to validate the method, while to date such detail is not to be found anywhere in the literature.A charge assignment method is developed to be applied to traditional 'continuously' doped regions in order to allow a consistent description of doping charge when combined with 'atomistic' doping assigned via the Cloud-In-Cell scheme. The charge assignment method also represents the only consistent description of electron charge assigned via CIC and the continuous doping charge.Trapping of a single electron in a series of scaled n-channel MOSFETs was studied with the ab initio Coulomb scattering method and is consistently seen to increase the Random Telegraph Signal, associated with the trapping and de-trapping of such charges, when compared with Drift-Diffusion simulations. It is seen that the electrostatic influence of the trapped charge is most prominent at low applied gate voltages where it accounts for nearly 70 - 80% of the total current reduction when including transport variation in devices with channel lengths of 30- \nm. At high gate voltages, transport variation is the dominant factor with the electrostatic impact accounting for only 40 - 60% of the total variation in the same devices.Extending this treatment to an ensemble of atomistic devices, it is seen that the inclusion of transport variations significantly increases the distribution in device parameters and that the transport variation is significantly dependent upon the specific dopant distribution. Within an ensemble of 50 'atomistic' devices, it was seen from Drift-Diffusion simulation that the average current showed a 3.0% increase over the continuously doped device, while Monte Carlo simulations resulted in a decrease in average current of 1.5%. The standard deviation of the current distribution from Drift-Diffusion simulations was 2.4% while, significantly, Monte Carlo simulations returned a value of 6.7%. This has implications for the published data obtained from Drift-Diffusion simulations which will underestimate the variation

Schottky Field Effect Transistors and Schottky CMOS Circuitry

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a bulk switching SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an increase in current injection with minimal process complexity. The different switching mechanism realized with this technique also reduces the ambipolar leakage current that has so often plagued SFETs of more conventional design. In addition, these devices have been utilized in a patent pending approach that may facilitate an increase in circuit density for devices of a given size. In other words, for example, it may be possible to achieve circuit density equivalent to 65 nm technology using a 90 nm process, while at the same time preserving or reducing local interconnect density for enhanced overall system speed. Fabrication details and electrical results will be discussed, as well as some initial modeling efforts toward gaining insight into the details of current injection at the metal-semiconductor (M-S) interface. The challenges faced using the ITS approach at aggressive scales will be discussed, as will the potential advantages and disadvantages of other approaches to SFET technology

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Vertical Integration of Germanium Nanowires on Silicon Substrates for Nanoelectronics.

Rapid development of semiconductor industry in recent years has been primarily driven by continuous scaling. As the size of the transistors approaches tens of nanometers, we are faced with challenges due to technological and economic reasons. To this end, unconventional semiconductor materials and novel device structures have attracted a lot of interests as promising candidates to replace the Si-channel MOSFET and help extend Moore’s law. In this dissertation, we focus on chemically-synthesized germanium nanowires, and investigate their potential as electronic devices, especially when vertically integrated on a Si substrate. The contributions of the work are as follows: First, the Vapor-Liquid-Solid method for growing Ge nanowires on (111) Si substrates is explored. In addition to the growth of vertical, taper-free, intrinsic Ge nanowires, strategies for doping the nanowires, forming a radial heterojunction and controlling growth sites are also discussed. Second, the Ge/Si heterojunction obtained via nanowire growth is examined by transmission electron microscopy. We confirm the epitaxial nature of the heterojunction despite the 4% lattice mismatch and determine the transition width to be 10-15 nm. Vertical heterodiodes with independently-tuned doping profile in both Ge and Si are demonstrated. Different devices are obtained, including: (1) a rectifying diode with >1,000,000 on/off ratio and ideality factor of 1.16; (2) a tunnel diode with room temperature negative differential resistance, peak current density of 4.57 kA/cm2 and reversed-bias tunnel current of 3.2 µA/µm; (3) a non-ohmic contact due to large valence band offset between Ge and Si. All observed behaviors are very well supported by theoretical analysis of the devices. In addition, a vertical junctionless transistor with Ge/Si core/shell nanowire channel and surrounding gate is demonstrated. High performance p-type transistor behavior with on state current density of 750 µA/µm and mobility of 282 cm2/V∙s is achieved. Moreover, an analytical model is developed to quantitatively explain the measured data and excellent agreement is obtained. Finally, progress towards the realization of a nanowire tunnel transistor is reported. A physical model for nanowire tunnel transistors is proposed. Preliminary experimental results verified that the device concept works although further optimization is still required to boost its performance.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120872/1/linchen_1.pd

Extended models of Coulomb scattering for the Monte Carlo simulation of nanoscale silicon MOSFETs

The International Technology Roadmap for Semiconductors (ITRS) specifies that MOSFET logic devices are to be scaled to sub-10nm dimensions by the year 2020, with 32nm bulk devices ready for production and double-gate FinFET devices demonstrated down to 5nm channel lengths. Future device generations are expected to have lower channel doping in order to reduce variability in devices due to the discrete nature of the channel dopants. Accompanying the reduced channel doping is a corresponding increase in the screening length, which is even now comparable with the channel length. Under such conditions, Coulomb scattering mechanisms become increasingly complex as the scattering potential interacts with a larger proportion of the device. Ionized impurity scattering within the channel is known to be an important Coulombic scattering mechanism within MOSFETs. Those channel impurities located close to the heavily doped source and drain or both, will induce a polarisation charge within the source and drain. These polarisation charge effects are shown in this work to increase the net screening of the channel impurities, due to the inclusion of remote screening effects, and significantly decrease the scattering rate associated with ionized impurity scattering. Remote screening can potentially reduce the control by ionized channel impurities over channel transport properties, leading to an increased sub-threshold current. A potential model has been obtained that is based on an exact solution of Poisson’s equation for an ionized impurity located close to one or both of these highly doped contact regions. The model shows that remote screening effects are evident within a few channel screening lengths of the highly doped contact regions. The resultant scattering model developed from this potential, which is based on the Born approximation, is implemented within a Monte Carlo simulator and is applied to MOSFET device simulation. The newly developed ionized impurity scattering model, which allows for remote screening, is applied in the simulation of two representative MOSFET devices: the first device being a bulk MOSFET device developed for the 32nm technology generation; the second device is an Ultra-Thin-Body Double Gate (UTB DG) MOSFET developed for the forthcoming 22nm technology generation. Thorough investigative simulations show that for both the bulk MOSFET and the UTB DG MOSFET, that remote screening of channel impurities in these devices is not a controlling effect. These results prove that the current model for ionized impurity scattering employed in Monte Carlo simulations is sufficient to model devices scaled to at least the 22nm technology node, predicted to be in production in the year 2012