Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

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Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate\u27s threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs)

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs)

Nanowires: Promising Candidates for Electrostatic Control in Future Nanoelectronic Devices

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Design and analytical performance of subthreshold characteristics of CSDG MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.The downscaling of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices have been the driving force for Nanotechnology and Very Large-Scale Integration (VLSI) systems. This is affirmed by Moore’s law which states that “The number of transistors placed in an Integrated Circuit (IC) or chip doubles approximately every two years”. The main objectives for the transistor scaling are: to increase functionality, switching speed, packing density and lower the operating power of the ICs. However, the downscaling of the MOSFET device is posed with various challenges such as the threshold roll-off, Drain Induced Barrier Lowing (DIBL), surface scattering, and velocity saturation known as Short Channel Effects (SCEs). To overcome these challenges, a cylindrically structured MOSFET is employed because it increases the switching speed, current flow, packing density, and provides better immunity to SCEs. This thesis proposes a Cylindrical Surrounding Double-Gate (CSDG) MOSFET which is an extended version of Double-Gate (DG) MOSFET and Cylindrical Surrounding-Gate (CSG) MOSFET in terms of form factor and current drive respectively. Furthermore, employing the Evanescent-Mode analysis (EMA) of a two-dimensional (2D) Poisson solution, the performance analysis of the novel CSDG MOSFET is presented. The channel length, radii Silicon film difference, and the oxide thickness are investigated for the CSDG MOSFET at the subthreshold regime. Using the minimum channel potential expression obtained by EMA, the threshold voltage and the subthreshold swing model of the proposed CSDG MOSFET are evaluated and discussed. The device performance is verified with various values of radii Silicon film difference and gate oxide thickness Finally, the low operating power and switching characteristics of the proposed CSDG MOSFET has been employed to design a simple CSDG bridge rectifier circuit for micropower electricity (energy harvester). Similar to the traditional MOSFETs, the switching process of CSDG MOSFET is in two operating modes: switch-ON (conduction of current between the drain and source) or switched-OFF (no conduction of current). However, unlike the traditional diode bridge rectifier which utilizes four diodes for its operation, the CSDG bridge rectifier circuits employs only two CSDGs (n-channel and p- channel) for its operation. This optimizes cost and improves efficiency. Finally, the results from the analyses demonstrate that the proposed CSDG MOSFET is a promising device for nanotechnology and self-micro powered device system application

Analytical Modeling of Ultrashort-Channel MOS Transistors

Les geometries de transistors d'avui són al rang de nanòmetres d'un sol dígit. En conseqüència, les funcionalitats dels dispositius es veuen afectades negativament pels efectes de canal curt i de mecànica quàntica (SCE i QMEs). Una transició de la geometria del transistor d'efecte de camp de tipus FinFET a Gate-All-Around (GAA) FETs com FETs de nanofils cilíndrics (NW) i de nanoplaques de silici (SiNS) es preveuen en els propers nodes tecnològics per suprimir els SCE i garantir una major miniaturització del MOSFET Aquesta dissertació se centra en el modelat analític de FETs de tipus NW i SiNS de canal ultracurt.S'introdueix un concepte de dimensions de doble porta (DG) equivalent per transferir un model de potencial de DG analític a FET de NW. Un model de corrent de DG compacte es modifica aprofitant la simetria rotacional dels FET de NW. L'efecte del confinament quàntic (QC) és implementat considerant l'eixamplament addicional de la banda prohibida al càlcul d'una concentració de portadors de càrrega intrínseca efectiva i al càlcul del voltatge llindar. L'efecte de corrent túnel directe de font a drenador (DSDT) a SiNS FET ultraescalats es modela amb el nou mètode de wavelets. Aquest model calcula analíticament la probabilitat de tunelització per a cada energia de l'electró, aproximant la forma de la barrera potencial mitjançant una barrera rectangular amb una altura de barrera equivalent. A causa de la fórmula de corrent túnel de Tsu-Esaki no analíticament integrable, es presenta un mètode analític anomenat model quasi-compacte (QCM). Aquest enfocament requereix, entre altres aproximacions, una iteració de Newton i una interpolació lineal de la densitat de corrent amb efecte túnel. A més, es realitza una anàlisi criogènica de temperatura i dopatge. S'investiga la forta influència de la distància del nivell de Fermi a la font des de la vora de la banda de conducció sobre el pendent subumbral, el corrent i la reducció de la barrera induïda per drenador (DIBL). A més, es demostra i explica la fusió de dos efectes relacionats amb el pendent subumbral i el DIBL. La validesa del concepte de dimensions DG equivalents es demostra mitjançant el mesurament i les dades de simulació de TCAD Sentaurus, mentre que el mètode de wavelets es verifica mitjançant simulacions NanoMOS NEGF.Las geometrías de transistores de hoy están en el rango de nanómetros de un solo dígito. En consecuencia, las funcionalidades de los dispositivos se ven afectadas negativamente por los efectos de canal corto y de mecánica cuántica (SCE y QMEs). Una transición de la geometría del transistor de efecto de campo de tipo FinFET a Gate-All -Around (GAA) FETs tales como FETs de nanohilos cilíndricos (NW) y de nanoplacas de silicio (SiNS) se prevén en los próximos nodos tecnológicos para suprimir los SCE y garantizar una mayor miniaturización del MOSFET. Esta disertación se centra en el modelado analítico de FETs de tipo NW y SiNS de canal ultracorto. Se introduce un concepto de dimensiones de doble puerta (DG) equivalente para transferir un modelo de potencial de DG analítico a FET de NW. Un modelo de corriente de DG compacto se modifica aprovechando la simetría rotacional de los FET de NW. El efecto del confinamiento cuántico (QC) es implementado considerando el ensanchamiento adicional de la banda prohibida en el cálculo de una concentración de portadores de carga intrínseca efectiva y en el cálculo del voltaje de umbral. El efecto de corriente túnel directa de fuente a drenador (DSDT) en SiNS FET ultraescalados se modela con el nuevo método de wavelets. Este modelo calcula analíticamente la probabilidad de tunelización para cada energía del electrón aproximando la forma de la barrera de potencial mediante una barrera rectangular con una altura de barrera equivalente. Usando la fórmula de corriente túnel de Tsu-Esaki no analíticamente integrable, se presenta un método analítico denominado modelo cuasi-compacto (QCM), querequiere una iteración de Newton y una interpolación lineal de la densidad de corriente de efecto túnel. Además, se realiza un análisis criogénico en temperatura y dopaje. Se investiga la fuerte influencia del nivel de Fermi de la fuente la sobre la pendiente subumbral, la corriente y la reducción del efecto DIBL. Además, se demuestra y explica la fusión de dos efectos relacionados con la pendiente subumbral y el DIBL. La validez del concepto de dimensiones DG equivalentes se demuestra mediante datos de mediciones y de simulaciones TCAD Sentaurus, mientras que el método de wavelets se verifica mediante simulaciones NanoMOS NEGF.Today's transistor geometries are in the single-digit nanometer range. Consequently, device functionalities are negatively affected by short-channel and quantum mechanical effects (SCEs & QMEs). A transition from fin field-effect transistor (FinFET) geometry to gate-all-around (GAA) FETs such as cylindrical nanowire (NW) and silicon nanosheet (SiNS) FETs is envisioned in the upcoming technology nodes to suppress SCEs and ensure further MOSFET miniaturization. This dissertation focuses on the analytical modeling of ultrashort-channel NW and SiNS FETs. An equivalent double-gate (DG) dimensions concept is introduced to transfer an analytical DG potential model to NW FETs. A compact DG current model is modified by exploiting the rotational symmetry of NW FETs. The effect of quantum confinement (QC) is implemented by considering the additional bandgap widening in the calculation of an effective intrinsic charge carrier concentration and in the calculation of the threshold voltage. The effect of direct source-to-drain tunneling (DSDT) current in ultrascaled SiNS FETs is modeled with the new wavelet approach. This model calculates the tunneling probability analytically for each electron energy by approximating the potential barrier shape by a rectangular barrier with an equivalent barrier height. Due to the nonanalytically integrable Tsu-Esaki tunneling formula an analytical approach named quasi-compact model (QCM) is presented. This approach requires, among other approximations, a Newton iteration, and a linear interpolation of the tunneling current density. Furthermore, a cryogenic temperature and doping analysis is performed. The strong influence of the distance of the source related Fermi level from the conduction band edge on the subthreshold swing, current, and drain-induced barrier lowering (DIBL) saturation is investigated. Also, the merging of two subthreshold swing and DIBL effects is demonstrated and explained. The validity of the equivalent DG dimensions concept is proven by measurement and TCAD Sentaurus simulation data, while the wavelet approach is verified by NanoMOS NEGF simulations

Analitical modeling for square gate-all-around MOSFETs

Two analytical models for square Gate All Around (GAA) MOSFETs has been introduced. The first part of this report include a quantum viewpoint and this first work has been published, while the second part approach a classical developed. With the model developed in the first part, it is possible to provide an analytical description of the 2D inversion charge distribution function (ICDF) in square GAA MOSFETs of difeerent sizes and for all the operational regimes. The accuracy of the model is verified by comparing the data with that obtained by means of a 2D numerical simulator that self-consistently solves the Poisson and Schrödinger equations. The expressions presented here are useful to achieve a good description of the physics of these transistors; in particular, of the quantization effects on the inversion charge. The analytical ICDF obtained is used to calculate important parameters from the device compact modeling viewpoint, such as the inversion charge centroid and the gate-to-channel capacitance, which are modeled for different device geometries and biases. The model presented accurately reproduces the simulation results for the devices under study and for different operational regimes. Anyway the second part of this report is focus on square GAA MOSFETs with a classical view point, which have not been analytically described in depth due to their particular geometrical complexity. The analytical description of cylindrical GAA MOSFETs is simpler since the symmetry of the structure around the rotation angle allows a 1D description, accounting just for the radial component. In the case of square GAA MOSFETs other modeling strategies are necessary, as will be shown below. Firstly, a technique to obtain analytical functions which are solutions of the 2D Poisson equation where the charge density in the silicon channel has been calculated, and the total inversion charge is introduced. Among all these functions a simple one for the electric potential in the silicon core of the square GAA MOSFETs was proposed. Secondly, the model introduced has been used to calculate the total inversion charge making use of Gauss's Law. The models obtained are finally validated with simulations data obtained with a 2D simulator developed in our group for Multiple-gate MOSFETs.Universidad de Granada. Departamento de Electrónica y Tecnología de los Computadores. Máster Métodos y Técnicas Avanzadas en Física (MTAF)This work was partially carried out within the framework of Research Projects of Department of Electronic and Computer Technology from the Faculty of Sciences, University of Granada

An analytical model for the inversion charge distribution in square GAA MOSFETs with rounded corners

In this work we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. With the model developed it is possible to provide an analytical description of the 2D inversion charge distribution function (ICDF) in devices of different sizes and for all the op erational regimes. The accuracy of the model is verified by comparing with data obtai ned by means of a 2D numerical simulator that self-consistently solves the Poi sson and Schr ̈odinger equations. The expressions presented here are useful to achieve a good d escription of the physics of these transistors; in particular, of the quantization effect s on the inversion charge. The analytical ICDF obtained is used to calculate important par ameters from the device compact modeling viewpoint, such as the inversion charge ce ntroid and the gate-to- channel capacitance, which are modeled for different device g eometries and biases.Universidad de Granada. Departamento de Electrónica y Tecnología de los Computadores. Máster Métodos y Técnicas Avanzadas en Física (MTAF)

A 2-D/3-D Schrödinger-Poisson Drift-Diffusion Numerical Simulation of Radially-Symmetric Nanowire MOSFETs

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