An Electrically Programmable Split-Electrode Charge-Coupled Transversal Filter (EPSEF)

A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated

1.5V fully programmable CMOS Membership Function Generator Circuit with proportional DC-voltage control

A Membership Function Generator Circuit (MFGC) with bias supply of 1.5 Volts and independent DC-voltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal output waveforms. HSPICE simulation results of the proposed circuit using the parameters of a double-poly, three metal layers, 0.5 μm CMOS technology validate the functionality of the proposed architecture, which exhibits a maximum deviation of the linearity in the programmability of 7 %

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Controller for computer control of brushless dc motors

A motor speed and torque controller for brushless d.c. motors provides an unusually smooth torque control arrangement. The controller provides a means for controlling a current waveform in each winding of a brushless dc motor by synchronization of an excitation pulse train from a programmable oscillator. Sensing of torque for synchronization is provided by a light beam chopper mounted on the motor rotor shaft. Speed and duty cycle are independently controlled by controlling the frequency and pulse width output of the programmable oscillator. A means is also provided so that current transitions from one motor winding to another is effected without abrupt changes in output torque

Automated Setup to Accurately Calibrate Electrical DC Voltage Generators

At National Institute of Metrological Research (INRIM), an automated setup to calibrate DC Voltage generators, mainly top-level calibrators from 1 mV to 1 kV has been developed. The heart of the setup is an INRIM-built automated fixed ratios DC Voltage divider. The significant achievement of this setup is the possibility to interconnect the divider, a DMM characterized in linearity, a DC Voltage Standard and a DC Voltage generator under calibration and automatically to manage the calibration process. This calibration method allows to save a lot of time, to improve the reliability and to increase the accuracy of the calibration of generators. The relative uncertainties of the system span from 0.6x10-6 to 1.2x10-4 improving the previous capabilities of the INRIM laboratory for calibration of programmable multifunction instruments. In addition, this system allows to avoid the employment of several Standards (some of them still manually operating) carrying out the entire process without changing the setup configuration and without the presence of operators. The concept of this setup can be transferred to secondary high-level electrical calibration Laboratories that could be consider it useful for their calibration activities.Comment: 6 pages 8 figure

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

Practical quantum realization of the ampere from the electron charge

One major change of the future revision of the International System of Units (SI) is a new definition of the ampere based on the elementary charge \emph{e}. Replacing the former definition based on Amp\`ere's force law will allow one to fully benefit from quantum physics to realize the ampere. However, a quantum realization of the ampere from \emph{e}, accurate to within $10^{-8}$ in relative value and fulfilling traceability needs, is still missing despite many efforts have been spent for the development of single-electron tunneling devices. Starting again with Ohm's law, applied here in a quantum circuit combining the quantum Hall resistance and Josephson voltage standards with a superconducting cryogenic amplifier, we report on a practical and universal programmable quantum current generator. We demonstrate that currents generated in the milliampere range are quantized in terms of $ef_\mathrm{J}$ ($f_\mathrm{J}$ is the Josephson frequency) with a measurement uncertainty of $10^{-8}$. This new quantum current source, able to deliver such accurate currents down to the microampere range, can greatly improve the current measurement traceability, as demonstrated with the calibrations of digital ammeters. Beyond, it opens the way to further developments in metrology and in fundamental physics, such as a quantum multimeter or new accurate comparisons to single electron pumps.Comment: 15 pages, 4 figure

A Modular Programmable CMOS Analog Fuzzy Controller Chip

We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-μm prototype which features an operation speed of 2.5 Mflips (2.5×10^6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.This work was supported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02- 02 (SIVA)

Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process