Design of reconfigurable RF circuits for self compensation

In this paper we will show how a combination of design choices allows for the design of a PVT robust RF front-end with minimum area, power and nominal specifications penalty.Peer ReviewedPostprint (published version

SELF-TUNING LOW-NOISE AMPLIFIER

A low-noise amplifier with a phase control loop is described in this paper. In the proposed circuit, the resonant frequency is auto-tuned to the input signal frequency. In that way, high gain (20 dB), a phase shift of -180o between input and output signals, and good selective characteristics are obtained. The amplifier is robust to parameter variations, ensuring maximal amplification of the input signal regardless of its frequency as long as it is within a specified frequency range (880-950 MHz). Hence, the proposed circuit possesses self-tuning properties. The stability of the phase loop is analyzed by using Lyapunov's control theory

Low temperature sensitivity CMOS transconductor based on GZTC MOSFET condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/ºC

ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

Characterization and Compensation of Thermal Effects in GaN HEMT Technologies

Further advancements with GaN based technologies relies on the ability to handle the heat flux, which consequently arises from the high power density. Advanced cooling techniques and thermal optimization of the technology are therefore prioritized research areas. Characterization techniques play a key role in the development of new cooling solutions, since these rely on accurate measurements of e.g. the temperature of the device. This thesis covers techniques to electrically characterize the lateral and vertical heat properties in GaN, and a temperature compensation technique for GaN MMICs.The first part outlines a methodology to electrically extract the thermal resistance of a GaN resistor without risking distortion from field induced electron trapping effects, which are exhibited by GaN heterostructures. The technique uses differential resistance measurements to identify a suitable resistor geometry, which minimizes trapping effects while enhancing the self-heating. Such conditions are crucial for electrical methods since these exploit the self- heating for a thermal analysis.Furthermore, a test structure and measurement method to electrically characterize the lateral heat spread was designed and evaluated. The structure is implemented with a thermal sensor, which utilizes the temperature-dependent IV characteristics of a GaN resistor, making it suitable for integration in GaN MMICs. The transient response can be obtained to extract the thermal time constants and propagation delay of the heat spread. At higher ambient temperatures, the propagation delay increases and the thermal coupling is increased. Lastly, a biasing technique to compensate for thermal degradation of the RF performance of an LNA was developed. By utilizing the gate- and drain voltage dependence of the RF performance, a constant gain against increasing temperature can e.g. be achieved

Rf Power Amplifier And Oscillator Design For Reliability And Variability

CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class E power amplifier is designed and laid out using TSMC 0.18 µm RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate selfheating effects under different localized heating situations. iv Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed

RF Circuit Designs for Reliability and Process Variability Resilience

Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits. In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation. Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation. Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design

Study and implementation of a PVT insensitive CMOS oscillator

Fallières Armand. Circulaire adressée aux Préfets, au sujet du classement des instituteurs. In: Bulletin administratif de l'instruction publique. Tome 47 n°891, 1890. pp. 137-138