Novel Rail Clamp Architectures and Their Systematic Design

abstract: Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

CDM Robust & Low Noise ESD protection circuits

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed. The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than 200,000 times without having major impact on the ESD performance. Also, the issue of noise coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation

Understanding, modeling, and mitigating system-level ESD in integrated circuits

This dissertation describes several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important tool for achieving quality designs quickly. However, modeling methodologies for system-level ESD are not yet mature. This dissertation aims to improve (i) simulation models of ESD protection elements, (ii) simulation models of ESD guns, and (iii) analytic models of rail-clamp circuits used for power-on ESD protection. Simulation models for two common ESD protection elements, diodes and silicon controlled rectifiers (SCR) are presented and evaluated, specifically with regard to the origins of poor voltage clamping. These models can be used for ESD network design and simulation; their applicability is not limited only to system-level ESD. Next, a circuit simulation model for an ESD gun (used to produce system-level ESD stresses) is presented. This model can be used for trouble-shooting and design. Lastly, an analytic model of rail-clamp circuits during system-level ESD is presented. These circuits can produce unstable oscillations or ringing on the supply; such problems must be eliminated during design. Analytic models help the designer understand how circuit parameters will impact the circuit’s performance. System-level ESD is a relatively new requirement being imposed on IC manufacturers; as such, current understanding of how system-level ESD affects ICs is not yet mature. This dissertation includes two studies that expand upon this knowledge. The first demonstrates that ground bounce due system-level ESD stress can lead to severe problems, including latch-up and power integrity problems. The second reports observations regarding input noise signals at an IC pin during system-level ESD stress. Lastly, this dissertation discusses experimental design of a test chip that will be manufactured shortly after this dissertation is completed. These experiments focus on observing and suppressing various errors that can occur during system-level ESD, arising from both noise at the inputs and power fluctuations. Additionally, this test chip includes standalone test structures that are used to reproduce power supply problems predicted in other sections of this dissertation

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process

Failures caused by supply fluctuations during system-level ESD

It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be caused by ESD-induced noise on signal inputs and power nets. Besides radiation, the current injection into the circuit alone can cause these disturbances, especially the sharp current spike of a high amplitude in system-level ESD. The waveform of this current is similar in various ESD test setups. Circuit models with distributed elements enable accurate modeling of the system-level ESD current in contact discharge. Experiments have shown that ESD-induced noise on signal traces starts to disturb the IO input at very low ESD levels, and the effectiveness of the transient voltage suppressor (TVS) on board is limited. The noise on supply is global to integrated circuit (IC), as it travels across all the power domains. The waveform of the noise depends on the polarity of the ESD current and the type of ESD protection. The experiments have shown that the supply fluctuation can be quite severe, as a strong reverse of the on-chip supply is indicated by monitor circuits starting from the ESD levels below the common required passing level. This poses a requirement of a minimum amount of on-chip decoupling capacitances (decaps) to limit the amplitude of supply fluctuations. This requirement is similar whether the supply voltage is generated on-chip or off-chip, as long as a large amount of off-chip decap is used and connected to the board ground. If the supply voltage is generated on-chip, the regulator needs to be carefully designed against ESD induced noise. In addition, the rail clamp, if not optimized, deteriorates the power integrity with its instability. The ESD-induced supply fluctuation may cause latch-up without careful attention to the well-bias scheme

Modeling and control of a high power soft-switched bi-directional DC/DC converter for fuel cell applications

This work presents a new high power, bi-directional, isolated dc-dc converter for a fuel cell energy management system that will be fitted into a test vehicle being built by Ford Motor Company. The work includes two parts. The first part is to propose a new topology and analyze the principles of the circuits operation. Design guidelines with detailed circuit simulations are presented to verify the feasibility of the new circuit topology. Based on the conceptual understanding of the converter, the mathematical model is also derived to design a control system that achieves soft start up and meets the performance requirements. The second part is to fabricate a 1.6 kW prototype converter in the laboratory. Using the prototype, the steady state performance of the open loop system was tested to verify the analysis and simulation results. A dual half-bridge topology is presented to implement the required power rating using the minimum number of devices. Unified zero-voltage-switching (ZVS) is achieved in either direction of power flow to eliminate switching losses for all devices, increase the efficiency of the system and reduce the electromagnetic interference (EMI). Compared to the other soft-switched dc-dc converters, neither a voltage-clamping circuit nor extra switching devices and resonant components are required in the proposed circuit for soft-switching implementation. All these new features allow efficient power conversion and compact packaging. Different start-up schemes are proposed to successfully limit the in-rush current when the converter is started in the boost mode of operation. The full control system including the start-up scheme is developed and verified using simulation results based upon the average model. A 1.6 kW prototype of the converter has been built and successfully tested under full power. The experimental results of the converter\u27s steady-state operation confirm the simulation analysis

Design, implementation, and verification of an FPGA-based control system for a permanent-magnet motor drive built upon a three-phase four-level active-clamped inverter

At the present time, a DE0 board from Terasic/Altera, which includes a Field Programmable Gate Array (FPGA) Cyclone III, is used to control a three-phase four-level active-clamped inverter which drives a permanent-magnet motor. The project consists in designing a new FPGA-based control system that substitutes the current control system based on the DE0 board. The novel control system will consist of a single board containing a new FPGA more suitable for the specific application, the analog-to-digital converters, and all the necessary auxiliary circuitry. The FPGA content wi[ANGLÈS] The present work summarizes the work and knowledge acquired by the author during its Master’s Thesis in the Research Group in Power Electronics, GREP. The development is based on the Multilevel Active-Clamped (MAC) power converter prototype, which was initially developed by GREP. Serving as a great introduction to the multilevel converter state-of-the-art, the prototype was tested and it was proved the need for a custom FPGA-based control platform board to drive a PMSM. The design of the board is then performed following the requirements established by the research group and the results obtained from the initial tests. Issues as power decoupling, signal conditioning and grounding strategies are discussed in the following chapters.[CASTELLÀ] La memoria aquí presentada recoge el trabajo y el conocimiento adquirido por el autor durante la elaboración de su tesis de Máster dentro del Grupo de Investigación en Electrónica de Potencia de la Universidad Politécnica de Cataluña, GREP. El trabajo elaborado se desarrolla en torno al prototipo, previamente desarrollado por los miembros del GREP, de un convertidor de potencia multinivel de tipo MAC (Multilevel Active-Clamped). La familiarización con los últimos avances en conversores multinivel se lleva a cabo mediante la fase de pruebas experimentales con este dispositivo, que a su vez demuestran la necesidad de diseñar una placa controladora específica basada en FPGA para mover un motor de imanes permanentes. Esta placa de control se diseña siguiendo los requisitos establecidos por el GREP y las necesidades surgidas en la fase de experimentación. En los capítulos del trabajo se tratan temas como el desacoplo de la alimentación, acondicionamiento de señales o metodologías de diseño de planos de masa.[CATALÀ] La memòria aquí presentada recull el treball i el coneixement adquirit per l'autor durant l'elaboració de la seva tesi de Màster dins del Grup de Recerca en Electrònica de Potència de la Universitat Politècnica de Catalunya, GREP. El treball es desenvolupa en torn al prototipus, prèviament desenvolupat pels membres del GREP, d'un convertidor de potència multinivell de tipus MAC (Multilevel Active-Clamped). La familiarització amb els darrers avanços en convertidors multinivell s'ha dut a terme mitjançant la fase de proves experimentals amb aquest prototipus, les quals han demostrat la necessitat de dissenyar una placa controladora específica basada en FPGA per controlar un motor d'imants permanents. Aquesta placa de control s'ha dissenyat seguint els requisits establerts pel GREP i les necessitats aparegudes en la fase d'experimentació. En els capítols del treball es tracten temes com el desacoblament de l'alimentació, condicionament de senyals o metodologies de disseny de plans de massa

On-die sensors for transient events

Failures caused by transient electromagnetic events like Electrostatic Discharge (ESD) are a major concern for embedded systems. The component often failing is an integrated circuit (IC). Determining which IC is affected in a multi-device system is a challenging task. Debugging errors often requires sophisticated lab setups which require intentionally disturbing and probing various parts of the system which might not be easily accessible. Opening the system and adding probes may change its response to the transient event, which further compounds the problem. On-die transient event sensors were developed that require relatively little area on die, making them inexpensive, they consume negligible static current, and do not interfere with normal operation of the IC. These circuits can be used to determine the pin involved and the level of the event in the event of a transient event affecting the IC, thus allowing the user to debug system-level transient events without modifying the system. The circuit and detection scheme design has been completed and verified in simulations with Cadence Virtuoso environment. Simulations accounted for the impact of the ESD protection circuits, parasitics from the I/O pin, package and I/O ring, and included a model of an ESD gun to test the circuit\u27s response to an ESD pulse as specified in IEC 61000-4-2. Multiple detection schemes are proposed. The final detection scheme consists of an event detector and a level sensor. The event detector latches on the presence of an event at a pad, to determine on which pin an event occurred. The level sensor generates current proportional to the level of the event. This current is converted to a voltage and digitized at the A/D converter to be read by the microprocessor. Detection scheme shows good performance in simulations when checked against process variations and different kind of events --Abstract, page iii