High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Design, implementation, and verification of an FPGA-based control system for a permanent-magnet motor drive built upon a three-phase four-level active-clamped inverter

At the present time, a DE0 board from Terasic/Altera, which includes a Field Programmable Gate Array (FPGA) Cyclone III, is used to control a three-phase four-level active-clamped inverter which drives a permanent-magnet motor. The project consists in designing a new FPGA-based control system that substitutes the current control system based on the DE0 board. The novel control system will consist of a single board containing a new FPGA more suitable for the specific application, the analog-to-digital converters, and all the necessary auxiliary circuitry. The FPGA content wi[ANGLÈS] The present work summarizes the work and knowledge acquired by the author during its Master’s Thesis in the Research Group in Power Electronics, GREP. The development is based on the Multilevel Active-Clamped (MAC) power converter prototype, which was initially developed by GREP. Serving as a great introduction to the multilevel converter state-of-the-art, the prototype was tested and it was proved the need for a custom FPGA-based control platform board to drive a PMSM. The design of the board is then performed following the requirements established by the research group and the results obtained from the initial tests. Issues as power decoupling, signal conditioning and grounding strategies are discussed in the following chapters.[CASTELLÀ] La memoria aquí presentada recoge el trabajo y el conocimiento adquirido por el autor durante la elaboración de su tesis de Máster dentro del Grupo de Investigación en Electrónica de Potencia de la Universidad Politécnica de Cataluña, GREP. El trabajo elaborado se desarrolla en torno al prototipo, previamente desarrollado por los miembros del GREP, de un convertidor de potencia multinivel de tipo MAC (Multilevel Active-Clamped). La familiarización con los últimos avances en conversores multinivel se lleva a cabo mediante la fase de pruebas experimentales con este dispositivo, que a su vez demuestran la necesidad de diseñar una placa controladora específica basada en FPGA para mover un motor de imanes permanentes. Esta placa de control se diseña siguiendo los requisitos establecidos por el GREP y las necesidades surgidas en la fase de experimentación. En los capítulos del trabajo se tratan temas como el desacoplo de la alimentación, acondicionamiento de señales o metodologías de diseño de planos de masa.[CATALÀ] La memòria aquí presentada recull el treball i el coneixement adquirit per l'autor durant l'elaboració de la seva tesi de Màster dins del Grup de Recerca en Electrònica de Potència de la Universitat Politècnica de Catalunya, GREP. El treball es desenvolupa en torn al prototipus, prèviament desenvolupat pels membres del GREP, d'un convertidor de potència multinivell de tipus MAC (Multilevel Active-Clamped). La familiarització amb els darrers avanços en convertidors multinivell s'ha dut a terme mitjançant la fase de proves experimentals amb aquest prototipus, les quals han demostrat la necessitat de dissenyar una placa controladora específica basada en FPGA per controlar un motor d'imants permanents. Aquesta placa de control s'ha dissenyat seguint els requisits establerts pel GREP i les necessitats aparegudes en la fase d'experimentació. En els capítols del treball es tracten temes com el desacoblament de l'alimentació, condicionament de senyals o metodologies de disseny de plans de massa

Embedded dynamic programming networks for networks-on-chip

PhD ThesisRelentless technology downscaling and recent technological advancements in three dimensional integrated circuit (3D-IC) provide a promising prospect to realize heterogeneous system-on-chip (SoC) and homogeneous chip multiprocessor (CMP) based on the networks-onchip (NoCs) paradigm with augmented scalability, modularity and performance. In many cases in such systems, scheduling and managing communication resources are the major design and implementation challenges instead of the computing resources. Past research efforts were mainly focused on complex design-time or simple heuristic run-time approaches to deal with the on-chip network resource management with only local or partial information about the network. This could yield poor communication resource utilizations and amortize the benefits of the emerging technologies and design methods. Thus, the provision for efficient run-time resource management in large-scale on-chip systems becomes critical. This thesis proposes a design methodology for a novel run-time resource management infrastructure that can be realized efficiently using a distributed architecture, which closely couples with the distributed NoC infrastructure. The proposed infrastructure exploits the global information and status of the network to optimize and manage the on-chip communication resources at run-time. There are four major contributions in this thesis. First, it presents a novel deadlock detection method that utilizes run-time transitive closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in NoCs. This detection scheme, TC-network, guarantees the discovery of all true-deadlocks without false alarms in contrast to state-of-the-art approximation and heuristic approaches. Second, it investigates the advantages of implementing future on-chip systems using three dimensional (3D) integration and presents the design, fabrication and testing results of a TC-network implemented in a fully stacked three-layer 3D architecture using a through-silicon via (TSV) complementary metal-oxide semiconductor (CMOS) technology. Testing results demonstrate the effectiveness of such a TC-network for deadlock detection with minimal computational delay in a large-scale network. Third, it introduces an adaptive strategy to effectively diffuse heat throughout the three dimensional network-on-chip (3D-NoC) geometry. This strategy employs a dynamic programming technique to select and optimize the direction of data manoeuvre in NoC. It leads to a tool, which is based on the accurate HotSpot thermal model and SystemC cycle accurate model, to simulate the thermal system and evaluate the proposed approach. Fourth, it presents a new dynamic programming-based run-time thermal management (DPRTM) system, including reactive and proactive schemes, to effectively diffuse heat throughout NoC-based CMPs by routing packets through the coolest paths, when the temperature does not exceed chip’s thermal limit. When the thermal limit is exceeded, throttling is employed to mitigate heat in the chip and DPRTM changes its course to avoid throttled paths and to minimize the impact of throttling on chip performance. This thesis enables a new avenue to explore a novel run-time resource management infrastructure for NoCs, in which new methodologies and concepts are proposed to enhance the on-chip networks for future large-scale 3D integration.Iraqi Ministry of Higher Education and Scientific Research (MOHESR)

Researching methods for efficient hardware specification, design and implementation of a next generation communication architecture

The objective of this work is to create and implement a System Area Network (SAN) architecture called EXTOLL embedded in the current world of systems, software and standards based on the experiences obtained during the ATOLL project development and test. The topics of this work also cover system design methodology and educational issues in order to provide appropriate human resources and work premises. The scope of this work in the EXTOLL SAN project was: • the Xbar architecture and routing (multi-layer routing, virtual channels and their arbitration, routing formats, dead lock aviodance, debug features, automation of reuse) • the on-chip module communication architecture and parts of the host communication • the network processor architecture and integration • the development of the design methodology and the creation of the design flow • the team education and work structure. In order to successfully leverage student know-how and work flow methodology for this research project the SEED curricula changes has been governed by the Hochschul Didaktik Zentrum resulting in a certificate for "Hochschuldidaktik" and excellence in university education. The complexity of the target system required new approaches in concurrent Hardware/Software codesign. The concept of virtual hardware prototypes has been established and excessively used during design space exploration and software interface design

RTRLIB : a high-level modeling tool for dynamically partially reconfigurable systems

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2020.Reconfiguração dinâmica parcial é considerada uma interessante técnica a ser aplicada para o aumento da flexibilidade de sistemas implementados em FPGA, em função da implementação dinâmica de módulos de hardware enquanto o restante do circuito permanece em operação. Trata- se de uma técnica utilizada em sistemas com requisitos muito restritos, como adaptabilidade, robustez, consumo de potência, custo e tolerância à falhas. Entretanto, a complexidade de desen- volvimento de sistemas com reconfiguração dinâmica parcial é consideravelmente alta quando comparada à de sistemas com lógica totalmente estática. Nesse sentido, novas metodologias e ferramentas de desenvolvimento são necessárias para reduzir a complexidade de implementação desse tipo de sistema. Nesse contexto, esse trabalho apresenta o RTRLib, uma ferramenta de modelagem em alto nível para o desenvolvimento de sistemas com reconfiguração dinâmica parcial em dispositivos Xilinx Zynq a partir da especificação e parametrização de alguns blocos. Sob condições específi- cas, o RTRLib automaticamante produz os scripts de hardware e software para implementação da solução utilizando o Vivado Design Suite e o SDK. Tais scripts são compostos pelos comandos necessários para a implementação do sistema desde a criação do projeto de hardware até a criação do arquivo de boot. Uma vez que o RTRLib é composto por IP-Cores previamente caracterizados, a ferramenta também pode ser utilizada para a análise, em fase de modelagem, do sistema a ser implementado, por meio da estimação de características importantes do sistema, como o consumo de recursos e latência. O presente trabalho também inclui novas funcionalidades implementadas no RTRLib no con- texto do design de hardware e de software, como: generalização do script de hardware, mapea- mento de IO, floorplanning por meio de uma GUI, criação de um gerador de script de software, gerador de template de aplicação standalone que faz uso do partial reconfiguration controller (PRC) e implementação de uma biblioteca para aplicações FreeRTOS. Por fim, quatro estudos de casos foram implementados para demonstrar as funcionalidades da ferramenta: um sistema de classificação de terrenos baseado em redes neurais, um sistema com regressores lineares utilizado para controle de uma prótese miocinética de mão e, por último, uma aplicação hipotética de um sistema com requisitos de tempo real.Partial dynamic reconfiguration is considered an interesting technique to increase flexibility in FPGA designs due to the dynamic replacement of hardware modules while the remainder of the circuit remains in operation. It is used in systems with hard requirements such as adaptability, robustness, power consumption, cost, and fault-tolerance. However, the complexity to develop dynamically partially reconfigurable systems in considerably higher comparing with static de- signs. Therefore, new design methodologies and tools have been required to reduce the design complexity of such systems. In this context, this work presents the RTRLib, a high-level modeling tool for the development of dynamically reconfigurable systems on Xilinx Zynq devices by a simple system specification and parametrization of some blocks. Under specific conditions, RTRLib automatically generates the hardware and software scripts to implement the solution using Vivado and SDK. These scripts are composed by the sequential design steps from hardware project creation to the boot image elaboration. Since RTRLib is composed of pre-characterized IP-Cores, the tool also can be used to analyze the system behavior during the design process by the early estimation of essential characteristics of the system such as resource consumption and latency. The present work also includes the new functionalities implemented on RTRLib in the context of the hardware and the software design, such as: hardware script generalization, IO mapping, floorplanning by a GUI, software script creation, generator of a standalone template application that uses PRC, and implementation of a FreeRTOS library application. Finally, four case studies were implemented to demonstrate the tool capability: a system for terrain classification based on neuron networks, a linear regressor system used to control a myokinetic-based prosthetic hand, and a hypothetical real-time application

Cyber-Physical Codesign of Wireless Structural Control System

Structural control systems play a critical role in protecting civil infrastructure from natural hazards such as earthquakes and extreme winds. Utilizing wireless sensors for sensing, communication and control, wireless structural control systems provide an attractive alternative for structural vibration mitigation. Although wireless control systems have advantages of flexible installation, rapid deployment and low maintenance cost, there are unique challenges associated with them, such as wireless network induced time delay and potential data loss. These challenges need to be considered jointly from both the network (cyber) and control (physical) perspectives. This research aims to develop a framework facilitating cyber-physical codesign of wireless control system. The challenges of wireless structural control are addressed through: (1) a numerical simulation tool to realistically model the complexities of wireless structural control systems, (2) a codesign approach for designing wireless control system, (3) a sensor platform to experimentally evaluate wireless control performance, (4) an estimation method to compensate for the data loss and sensor failure, and (5) a framework for fault tolerance study of wireless control system withreal-time hybrid simulation. The results of this work not only provide codesign tools to evaluate and validate wireless control design, but also the codesign strategies to implement on real-world structures for wireless structural control