Stepper microactuators driven by ultrasonic power transfer

Advances in miniature devices for biomedical applications are creating ever-increasing requirements for their continuous, long lasting, and reliable energy supply, particularly for implanted devices. As an alternative to bulky and cost inefficient batteries that require occasional recharging and replacement, energy harvesting and wireless power delivery are receiving increased attention. While the former is generally only suited for low-power diagnostic microdevices, the latter has greater potential to extend the functionality to include more energy demanding therapeutic actuation such as drug release, implant mechanical adjustment or microsurgery. This thesis presents a novel approach to delivering wireless power to remote medical microdevices with the aim of satisfying higher energy budgets required for therapeutic functions. The method is based on ultrasonic power delivery, the novelty being that actuation is powered by ultrasound directly rather than via piezoelectric conversion. The thesis describes a coupled mechanical system remotely excited by ultrasound and providing conversion of acoustic energy into motion of a MEMS mechanism using a receiving membrane coupled to a discrete oscillator. This motion is then converted into useful stepwise actuation through oblique mechanical impact. The problem of acoustic and mechanical impedance mismatch is addressed. Several analytical and numerical models of ultrasonic power delivery into the human body are developed. Major design challenges that have to be solved in order to obtain acceptable performance under specified operating conditions and with minimum wave reflections are discussed. A novel microfabrication process is described, and the resulting proof-of-concept devices are successfully characterized.Open Acces

Profile simulations of plasma etching of silicon under consideration of charging effect and cryogenic condition

Diese Arbeit befasst sich mit der Simulation von Plasmaätz-Prozessen zur Erzeugung vonHAR-Strukturen (engl.: "high aspect ratio") in Silizium. Plasmaätz-Technologie spielt eine kritischeRolle für die Herstellung mikroelektronischer Geräte und mikro-/nano-elektromechanischerSysteme (M(N)EMS). Aufgrund der Komplexität physikalischer und chemischer Phänomene,welche während der Prozessierung im Plasmareaktor auftreten, ist die Technologie noch nichtvollständig verstanden. Simulationssoftware kann einen wesentlichen Beitrag zu deren Untersuchungleisten, indem sie Zeit und Kosten für eine Vielzahl von Experimenten zur Entwicklung vonPlasmaätz-Prozessen reduziert. Der ViPER Simulator, der am Fachgebiet MNES der TechnischenUniversität Ilmenau entwickelt wurde, ermöglicht die Durchführung virtueller Experimente, indenen verschiedene sekundäre Effekte des Plasmaätzens zum besseren Verständnis des Prozessesberücksichtigt und analysiert werden können. In der vorliegenden Arbeit wurden neue Modellefür ViPER entwickelt, die folgenden Zielstellungen hatten: 1) Simulation des Einflusses von lokalerAufladung (engl.: "charging effect") auf das entstehende Oberflächenprofil; 2) Simulationvon kryogenischem HAR-Plasmaätzen von Silizium.Erstmalig wurde der Einfluss der lokalen Aufladung an dielektrischen Oberflächen der Mikrostrukturenauf das entstehende Oberflächenprofil über die gesamte Dauer des Ätzprozessessimuliert und gleichzeitig mit den Ergebnissen realer Experimente validiert. Das Modell simuliertden Transport von geladenen Teilchen im Bereich der prozessierten Mikrostruktur unter Berücksichtigunglokaler elektrischer Felder, die durch den erwähnten Aufladungseffekt erzeugt werden.Durch die Nutzung der Finite-Elemente-Methode (FEM) zur Berechnung des elektrischenFeldes kann das Modell sehr gut mit komplexer Geometrie des betrachteten Bereichs umgehen,welche häufig während der Simulation auftritt. Falls nötig, kann das Modell elektrische Felderauch in dielektrischen Materialien der prozessierten Probe berücksichtigen. Teilchentrajektorienwerden analytisch anhand des FEM-Netzes berechnet. Zur Validierung des Modells wurde einHAR-Ätzexperiment auf Basis eines SF6/C4F8-Gas-Chopping-Prozesses genutzt. Das Modellist allgemein und kann auf viele Ätzchemien angewendet werden.Zum ersten Mal wurde ein Niedertemperatur-SF6/O2-Plasmaätzprozess von Nanostrukturen(Linienbreite 35 nm) in Silizium unter Verwendung eines im Rahmen dieser Arbeit entwickeltenKryo-Ätzmodells simuliert. Die Ergebnisse boten eine gute Übereinstimmung mit experimentellenDaten. Das entwickelte Modell ist folglich ein sehr attraktives Werkzeug für die weitere Erforschungund Entwicklung der HAR-Nanostrukturierung unterhalb 10 nm. Es liefert Simulationenim Mikrostrukturbereich ohne das Plasma in der gesamten Reaktorkammer zu modellieren. Daherwurden viele Modellparameter geschätzt und kalibriert (die entstehenden Plasmaspezies undderen Flüsse zur Waferoberfläche, Winkel- und Energieverteilungen von einfallenden Ionen ander Probenoberfläche, etc.). Zu diesem Zweck wurde in Kooperation mit dem Lawrence BerkeleyNational Lab (Kalifornien, USA) eine Vielzahl von Experimenten durchgeführt. Die internen Modellparameterwurden bestimmt, indem kryogenisches HAR-Ätzen (-120C, Linienbreite 1,5–0,5um) mit verschiedenen Ätzrezepten simuliert und mit Experimentaldaten verglichen wurde.This work focuses on simulations of plasma etching of high aspect ratio (HAR) structures insilicon. Plasma etching technology plays a critical role for the production of microelectronic devices,and micro- and nanoelectronic systems (M(N)EMS). Due to the great complexity of physicaland chemical phenomena occurring in the plasma reactor during the processing, plasma etchingtechnique is still not fully understood. Economizing time and costs needed for numerous experimentsin the context of the process development, simulation software can significantly help in thedetailed investigation of the technology. ViPER simulator, developed by the MNES group at IlmenauUniversity of Technology, allows conducting virtual experiments where various secondaryeffects of plasma etching can be considered and analyzed for better insight into the process. In terms of the presented work, new models were developed for the ViPER, to address the followingtwo objectives: 1) simulation of the influence of local surface charging (charging effect) on theevolving feature profile; 2) simulation of cryogenic HAR silicon plasma etching.For the first time, by utilizing the charging effect simulation model developed in this work, theinfluence of local charging of the microstructure insulating surfaces on the evolving feature profilewas simulated over the entire course of the etching process and, at the same time, the obtainedresults were validated by comparison with real plasma etching experiment. The model simulatestransport of charged particles in the intra-feature area accounting for the influence of local electricfield induced by the local surface charging. By using finite element method (FEM) for electric fieldcalculation, the model is able to handle complicated geometry of the area of interest which canoften arise during the simulations. If needed, the developed model can also allow for electric fieldin the insulating materials of the sample. The particle trajectories are analytically calculated usingthe FEM mesh. A HAR etching experiment, employing a SF6/C4F8 gas chopping process, wasused for the validation. The model is general and can be applied across many etching chemistries.For the first time, by using the developed in this work cryogenic silicon etching model, alow-temperature SF6/O2 plasma etching of nano-features (linewidth 35 nm) in silicon was simulated.The obtained results were tested with the real experimental data, showing a good agreement.Hence, the developed model is a very attractive tool for further research and developmentof sub-10 nm HAR nano patterning. The model provides feature scale (in the microstructure area)simulations without modelling the plasma within the entire reactor chamber. Thus, many of themodel parameters (the arising plasma species, the plasma species’ fluxes to the wafer, ion angularand energy distributions at the sample, sticking coefficients of plasma species arriving at the targetsurface, etc.) were assessed and calibrated. To this end, a large number of experiments wasconducted in cooperation with the Lawrence Berkeley National Laboratory, California, USA. Theinternal model parameters were estimated by calibrations, where, using different configurations ofplasma etch equipment parameters, cryogenic (-120C) HAR etching of micro-features (1.5–0.5um) was simulated and tested with the corresponding experimental data

A nano-tensile testing system for studying nanostructures inside an electron microscope:design, characterization and application

Mechanical properties of nanostructures could be remarkably different from their bulk counterparts owing to scale effects, which have attracted considerable research interest in recent years. However, nanomechanics studies are hindered by the difficulties of conducting well-instrumented mechanical testing. The objective of this thesis is to develop a novel tensile stage that can be used to probe mechanical properties of universal one-dimensional (1D) nanostructures, like nanowires and nanotubes, inside a scanning/transmission electron microscope (SEM/TEM). The main challenges of performing tensile tests at the nanoscale are: (1) specimen alignment and fixation on the tensile stage; (2) application and measurement of tensile force with nano-Newton resolution; (3) measurement of specimen elongation with nanometer resolution. Previous studies have shown that micro-electromechanical system (MEMS) technology combined with advanced microscopy (e.g. SEM and TEM) provides promising perspectives to address these challenges. Two types of nano-tensile stages, fabricated in a silicon on insulator (SOI) wafer, were developed in this thesis, which consisted of a comb-drive actuator and either a differential capacitive force sensor or a double clamped beam force sensor. The optimized comb-drive actuators could output an in-plane force of about 210 µN at a drive voltage of 120 V, and the force sensors achieved resolutions of better than 50 nN. Individual 1D nanostructures were placed on the MEMS device by in-situ nanomanipulations and fixed at their two ends via focused electron beam induced deposition (FEBID). A strategy of modifying device topography, e.g. in the form of trenches or pillars, was proposed to facilitate the specimen preparation by in-situ manipulation that could achieve a high yield of about 80%. The mechanical testing function of the developed micro devices was demonstrated by tensile tests on individual Co and Si nanowires (NWs) inside an SEM. The average apparent Young's modulus, tensile strength and fracture strain of the electrochemically deposited Co NWs were measured to be (75.3±14.6) GPa, (1.6±0.4) GPa and (2.2±0.6) %, respectively. The measured Young's modulus is significantly lower than that of Co in the bulk form (209 GPa), which is likely caused by structural defects (e.g. pores) and surface effects (e.g. surface contaminations and surface oxide layers). The phosphorous-doped SiNWs grown bottom up by the vapor-liquid-solid (VLS) technique showed an average Young's modulus of (170.0±2.4) GPa and a tensile strength larger than 8.3 GPa. This finding confirms that materials strength increases as their sizes scale down. The top down electroless chemically etched Si NWs show a tensile strength of 5.4 GPa. The developed MEMS devices and experimental techniques enable an alternative way of in-situ nanomechanical characterization based on electron microscopy. The design methodology and learning presented in this thesis would be useful to develop nano-tensile stages of other configurations with more advanced functions

Silicon dry etching using fluorine-based gas for nanoscale cone and grating structure fabrication

Dry etching technique is widely used in creating high aspect ratio nanostructures currently. This pattern transfer process has better performance in the profile controlling compared with wet etching technique. For the plasma etching, fluorine-based plasmas are mainly used for rapid isotropic silicon etching process. To achieve an anisotropic profile, SF6/C4F8 and SF6/O2 are generally used in the etching process. These anisotropic profiles, such as cones and pillars, are widely used in photovoltaic and optoelectronic devices. However, current research related to cone structure fabrication are a more random process. The size of the profile cannot be precisely controlled. Although there are some recipes can result in a taper profile, but large amount of C4F8 gas also inhibits further etching. In addition, the etching process with the mixture of C4F8 and SF6 gases always raises the concern about chamber contamination issues. In this thesis, some solutions are proposed to solve such problems. The traditional pseudo-Bosch process has been optimized by introducing a periodical oxygen clean step to remove the fluorocarbon polymer deposition during process. The cone array of a controllable size is fabricated by combining with optimized pseudo-Bosch process and maskelss etching. Another two ways of fabricating cone array are also introduced which are shrinking SiO2 mask and photoresist mask. Unlike SiO2 masks that spontaneously form a tapered structure when they are almost consumed, photoresist masks can be manually applied oxygen plasma to shrink periodically for a controllable cone array fabrication. In addition, the detailed investigation of near room temperature SF6/O2 etching is presented to prove it is possible to be an alternative way of pseudo-Bosch process in cone or grating structure fabrication

Advanced Plasma Processing: Etching, Deposition, and Wafer Bonding Techniques for Semiconductor Applications

Plasma processing techniques are one of the cornerstones of modern semiconductor fabrication. Low pressure plasmas in particular can achieve high radical density, high selectivity, and anisotropic etch profiles at low temperatures and mild voltages. This gentle processing environment prevents unwanted diffusion and degradation of materials due to heat and lattice damage from ion bombardment. Plasma treatments have a minimal effect on existing wafer structure, which is a key requirement for large scale integration schemes such as CMOS. In addition, recent progress in plasma-assisted wafer bonding has demonstrated low temperature, low pressure recipes utilizing O_2 plasma surface treatment for joining dissimilar semiconductor materials, such as silicon (Si) and indium phosphide (InP) (Fang et al., 2006)

Développement et caractérisation des procédés de gravure plasma impliqués dans la réalisation de grille métallique de transistor pour les technologies FDSOI 14nm : contrôle dimensionnel et rugosité de bord

In a transistor manufacturing process, patterning is one of the hardest stages to control. Along with downscaling, the specifications for a transistor manufacturing have tightened up to the nanometer scale. Extreme metrology and process control are required and Critical Dimension Uniformity (CDU) and Line Width Roughness (LWR) have become two of the most important parameters to control.So far, to meet the requirements of the latest CMOS technologies, post-lithography treatments such as plasma cure treatments have been introduced to increase photo-resist stability and to improve LWR prior to pattern transfer. However, conventional post-lithography treatments are no more efficient to address the specifications of14nm gate patterning where more complicated designs are involved.In this work, we have studied limitations of cure pretreatments in 2D gate integrations. In fact, the HBr plasma post-lithography treatment was identified as being responsible of a local pattern shifting that result in a loss of the device’s electrical performance. Preliminary results show that, cure step removal helps to control pattern shifting but to the detriment of the LWR. Indeed, if no cure treatment is introduced in the gate patterning process flow, photoresist patterns undergo severe stress during the subsequent Si-ARC plasma etching in fluorocarbon based plasmas. In this work, the mechanisms that drive such resist degradation in fluorocarbon plasmas have been studied and improved SiARC etch process condition shave been proposed. Besides, we evaluate how the state-of-art gate etch process can be improved, by investigating the impact of each plasma etching step involved in the high-K metal gate patterning on both LWR and gate shifting. The goal of this study is to determine if the TiN metal gate roughness can be modified by changing the gate etch process conditions. Our research reveals that addition of N2 flash steps prevents from gate profile degradation and sidewall roughening. In revenge, the TiN microstructure as well as the HKMG etch process has no impact on the gate final roughness. The hard mask patterning process remains the main contributor for gate roughening.Dans le procédé d'élaboration d'un transistor, la définition des motifs de grilles est une des étapes les plus dures à contrôler. Avec la miniaturisation des dispositifs, les spécifications définies pour la structuration des transistors se sont resserrées jusqu'à l'échelle du nanomètre. Ainsi, le Contrôle Dimensionnel(CD) et la rugosité de bord des lignes (LWR) sont devenus les paramètres les plus importantes à contrôler. Précédemment, pour atteindre les objectifs définis pour les précédentes technologies CMOS, des traitements post-lithographiques tels que les traitements plasma à base d’HBr ont été introduits pour améliorer la résistance des résines aux plasmas de gravure et minimiser la rugosité des motifs de résine avant leur transfert dans l’empilement de grille. Cependant, ces méthodes conventionnelles ne sont plus satisfaisantes pour atteindre les spécifications des nœuds avancés 14FDSOI, qui font intervenir des schémas complexes d’intégration de motifs. Dans ces travaux, les limitations des traitements plasma HBr pour réaliser des motifs de grille bidimensionnels comme définis par les règles de dessin ont été mises en évidence. . En effet, il s’avère que les traitements par plasma HBr sont responsables d'un déplacement local du motif de grille, qui entraine sur le produit final une perte de rendement. Des résultats préliminaires montrent que le retrait de cette étape de traitement améliore le phénomène de décalage des grilles, au détriment de la rugosité des motifs de résines. En effet, les résines non traités par plasma subissent d’importantes contraintes lors de l’ étape de gravure SiARC en plasma fluorocarbonnés, ce qui génère une nette augmentation de la rugosité de la résine qui se transfère par la suite dans les couches actives du dispositif. Dans cette thèse, j’ai étudié les mécanismes de dégradation des résines dans des plasmas fluorocarbonés. Cette compréhension a abouti au développement d’une nouvelle chimie de gravure plasma de la couche de SiARC qui limite la dégradation des résines. De plus, j’ai évalué comment le procédé complet de gravure de grille métallique peut être amélioré pour éliminer la rugosité et la déformation des motifs en travaillant sur chacune des étapes impliquées. Le but de cette étude est d’identifier les étapes de gravure ayant un rôle dans la rugosité finale de la grille. Mes travaux montrent que l'ajout des étapes de nitruration limite la dégradation du profil de grille et de la rugosité des flancs. Au contraire, la microstructure du film de TiN ainsi que les procédés de gravure de grille métal n'ont pas d'impact sur la rugosité finale du dispositif. Le transfert du motif de grille lors des étapes de gravure du masque dur reste toujours le principal contributeur de la rugosité finale de grille

Design and Implementation of Silicon-Based MEMS Resonators for Application in Ultra Stable High Frequency Oscillators

The focus of this work is to design and implement resonators for ultra-stable high-frequency ( \u3e 100MHz) silicon-based MEMS oscillators. Specifically, two novel types of resonators are introduced that push the performance of silicon-based MEMS resonators to new limits. Thin film Piezoelectric-on-Silicon (TPoS) resonators have been shown to be suitable for oscillator applications due to their combined high quality factor, coupling efficiency, power handling and doping-dependent temperature-frequency behavior. This thesis is an attempt to utilize the TPoS platform and optimize it for extremely stable high-frequency oscillator applications. To achieve the said objective, two main research venues are explored. Firstly, quality factor is systematically studied and anisotropy of single crystalline silicon (SCS) is exploited to enable high-quality factor side-supported radial-mode (aka breathing mode) TPoS disc resonators through minimization of anchor-loss. It is then experimentally demonstrated that in TPoS disc resonators with tethers aligned to [100], unloaded quality factor improves from ~450 for the second harmonic mode at 43 MHz to ~11,500 for the eighth harmonic mode at 196 MHz. Secondly, thickness quasi-Lamé modes are studied and demonstrated in TPoS resonators for the first time. It is shown that thickness quasi-Lamé modes (TQLM) could be efficiently excited in silicon with very high quality factor (Q). A quality factor of 23.2 k is measured in vacuum at 185 MHz for a fundamental TQLM-TPoS resonators designed within a circular acoustic isolation frame. Quality factor of 12.6 k and 6 k are also measured for the second- and third- harmonic TQLM TPoS resonators at 366 MHz and 555 MHz respectively. Turn-over temperatures between 40 °C to 125 °C are also designed and measured for TQLM TPoS resonators fabricated on degenerately N-doped silicon substrates. The reported extremely high quality factor, very low motional resistance, and tunable turn-over temperatures \u3e 80 °C make these resonators a great candidate for ultra-stable oven-controlled high-frequency MEMS oscillators

Copper Electrodeposition in Mesoscale Through-Silicon-Vias

Copper (Cu) electrodeposition (ECD) in through-silicon-vias (TSVs) is an essential technique required for high-density 3-D integration of complex semiconductor devices. The importance of Cu ECD in damascene interconnects has led to a natural development towards copper electrodeposition in TSVs. Cu ECD is preferred over alternative approaches like the chemical vapor deposition (CVD) of tungsten (W) or aluminum (Al) because Cu ECD films have lower film stress, lower processing temperatures, and more optimal thermal and electrical properties as compared with CVD W or Al. Via filling with electroplated Cu on substrates that have undergone atomic layer deposition of a conformal platinum seed metal is investigated herein. These mesoscale vias (600 μm depth, 5:1 aspect ratio) will be utilized in ultra-high-vacuum systems and thus require a uniform, void-free Cu deposit of sufficient thickness to prevent device degradation due to skin effects when RF frequencies as high as 100 V at 100 MHz are used. Conformally Cu-lined TSVs are achieved through the implementation of a complex ECD parameter scheme, and these results are compared with computational finite element modeling (FEM) outcomes. A novel, single additive chemistry is also developed and implemented to achieve fully filled void-free mesoscale TSVs within 6 hours of plating time, which represents an extraordinarily fast and controllable plating rate (100 μm/hour) for interconnect (IC) feature filling

Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

A nanostructured porous silicon based drug delivery device

Targeted and controlled delivery of therapeutic agents on demand is pivotal in realising the efficacy of many pharmaceuticals. The design and fabrication of a novel, electrically-addressable, porous structure-based drug delivery device for the controlled release of therapeutic proteins and peptides, are described in this thesis. The initial prototype microdevice design incorporates a porous polysilicon (PPSi) structure as a drug reservoir. Two alternative methods were investigated to fabricate the PPSi structure: i) the chemical stain etching method; ii) a reactive ion etching (RIE) method through a masking template. Random pores, with irregular pore shape and size in the micro- to mesoporous regime (< 50 nm), were obtained using the stain etching method but this method suffered from poor reproducibility and non-uniformity. Two novel RIE approaches were investigated to fabricate ordered PPSi structures; two different masking templates were investigated – a porous anodic alumina (PAA) and a metal mask with hexagonally arranged holes produced by a novel nanosphere lithography (NSL) technique. A quasi-ordered PAA template with pore diameters in the region of 50 nm was fabricated but was not suitable for the subsequent proposed RIE process. By using the NSL technique, quasi-ordered PPSi structures with tapered pore profiles, were obtained. This is the first demonstration of the fabrication of PPSi with ordered pores of sizes in the macropore range of ~ 370 nm.A revised silicon-based prototype microdevice was designed and fabricated. The microdevice incorporates a nanostructured, quasi-ordered porous silicon (PSi) as a drug reservoir and an integrated heater and temperature sensor as an active control mechanism. The PSi structure was fabricated using a modified NSL technique and a Bosch-based RIE process. Hexagonally arranged cylindrical pores with diameters between ~75 nm and ~120 nm, and depths in the range of ~330 nm and 500 nm, were obtained. The novel fabrication techniques investigated here are simple and versatile; both p-type and n-type PSi structures have been successfully fabricated. Proof-of-concept studies, using the revised prototype drug delivery microdevices, suggested that the nanostructured PSi would be suitable for the passive release of an intermediate-sized (~23,000 Dalton) model protein. It is envisaged that the microdevice has the potential to deliver osteoinductive growth factors, on demand, to the site of fracture, in a controlled and sustainable manner, as a first step to an intelligent therapeutic system for skeletal regeneration