Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

Digital design techniques for dependable High-Performance Computing

L'abstract è presente nell'allegato / the abstract is in the attachmen

Design for testability of a latch-based design

Abstract. The purpose of this thesis was to decrease the area of digital logic in a power management integrated circuit (PMIC), by replacing selected flip-flops with latches. The thesis consists of a theory part, that provides background theory for the thesis, and a practical part, that presents a latch register design and design for testability (DFT) method for achieving an acceptable level of manufacturing fault coverage for it. The total area was decreased by replacing flip-flops of read-write and one-time programmable registers with latches. One set of negative level active primary latches were shared with all the positive level active latch registers in the same register bank. Clock gating was used to select which latch register the write data was loaded to from the primary latches. The latches were made transparent during the shift operation of partial scan testing. The observability of the latch register clock gating logic was improved by leaving the first bit of each latch register as a flip-flop. The controllability was improved by inserting control points. The latch register design, developed in this thesis, resulted in a total area decrease of 5% and a register bank area decrease of 15% compared to a flip-flop-based reference design. The latch register design manages to maintain the same stuck-at fault coverage as the reference design.Salpaperäisen piirin testattavuuden suunnittelu. Tiivistelmä. Tämän opinnäytetyön tarkoituksena oli pienentää digitaalisen logiikan pinta-alaa integroidussa tehonhallintapiirissä, korvaamalla valitut kiikut salpapiireillä. Opinnäytetyö koostuu teoriaosasta, joka antaa taustatietoa opinnäytetyölle, ja käytännön osuudesta, jossa esitellään salparekisteripiiri ja testattavuussuunnittelun menetelmä, jolla saavutettiin riittävän hyvä virhekattavuus salparekisteripiirille. Kokonaispinta-alaa pienennettiin korvaamalla luku-kirjoitusrekistereiden ja kerran ohjelmoitavien rekistereiden kiikut salpapiireillä. Yhdet negatiivisella tasolla aktiiviset isäntä-salpapiirit jaettiin kaikkien samassa rekisteripankissa olevien positiivisella tasolla aktiivisten salparekistereiden kanssa. Kellon portittamisella valittiin mihin salparekisteriin kirjoitusdata ladattiin yhteisistä isäntä-salpapireistä. Osittaisessa testipolkuihin perustuvassa testauksessa salpapiirit tehtiin läpinäkyviksi siirtooperaation aikana. Salparekisterin kellon portituslogiikan havaittavuutta parannettiin jättämällä jokaisen salparekisterin ensimmäinen bitti kiikuksi. Ohjattavuutta parannettiin lisäämällä ohjauspisteitä. Salparekisteripiiri, joka suunniteltiin tässä diplomityössä, pienensi kokonaispinta-alaa 5 % ja rekisteripankin pinta-alaa 15 % verrattuna kiikkuperäiseen vertailupiiriin. Salparekisteripiiri onnistuu pitämään saman juuttumisvikamallin virhekattavuuden kuin vertailupiiri

A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter

Modern application processors (microprocessors and Digital Signal Processors) are power hungry and demand power management solutions that can withstand their frequent and high slew-rate load transients while regulating their supply in a tight voltage tolerance. Hysteretic converter has excellent transient response performance but its variable switching frequency causes concern for electromagnetic interference in noise sensitive applications. A new frequency stabilization scheme for hysteretic buck dc-dc converters is proposed in this thesis. The equivalent series resistance (ESR) of the output capacitor is regulated by a phase-locked loop (PLL) to stabilize the operating frequency of the converter. The proposed fixed frequency ESR-controlled converter achieves a fixed 2MHz switching frequency, with less than 1µs response time to a 500mA load step while limiting undershoot and overshoot on the output voltage to 50mV and 40mV respectively. The performance of the presented work shows that the ESR of the output capacitor of a Hysteretic Buck Converter can be controlled to stabilize the switching frequency of the Hysteretic DC-DC Converter

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Low-Power 12-bit Quasi-Passive Segmented DAC Implemented in 130nm CMOS Technology

This thesis work proposes a low-power 12-bit digital-to-analog converter (DAC) designed in a 130nm process. The DAC to be presented is of a segmented design where the architecture is split into pipelined and thermometer coded segments. This allows for high linearity and low distortion while maintaining high speed and low area. Since the DAC will be utilize a switched capacitor design, an output buffer stage is added to allow for a wide range of loads. Correlated double sampling (CDS) and correlated level shifting (CLS) are implemented to relax operational amplifier specifications and improve buffer performance. Data weighted averaging (DWA) is implemented to mitigate capacitor mismatch errors due process limitations in fabrication. Static and dynamic simulations are performed as well as mismatch sensitivity analyzed

InP microdisks for optical signal processing and data transmission

The performance increase in telecommunication and computing systems demands an ever increasing input-output (IO) bandwidth and IO density, which can be met by integrated photonics. Using photonic integration, much higher densities of optical components can be achieved allowing for short-range optical communication systems in, e.g., high performance computers. The key functionalities required for these optical communication systems are light generation, light modulation and light detection. In addition to this other functionalities are also desirable, such as wavelength conversion. This thesis highlights the design and fabrication of indium phosphide (InP) microdisks heterogeneously integrated on silicon-on-insulator substrates. The fabrication of the microdisks in a laboratory clean-room environment is described. These devices can fulfil the above-mentioned functions required in optical communication. Experiments are then performed on the fabricated devices dealing with these various functionalities that are required for optical communication. The lasing properties of the devices are shown and simulated with a spatiallydependent rate equation model accurately predicting the device behaviour. A detailed speed analysis is given, including a parameter extraction of the devices. The operation of the devices as detectors is highlighted. Furthermore the PhD thesis provides a deep analysis of the use of InP microdisks as modulators. Besides the forward-biased operation principle using the free-carrier plasma-dispersion effect, also a high-speed reversely biased operation mode is proposed and demonstrated experimentally. The thesis also describes various approaches on how to improve the performance of the devices, in particular when using them as lasers. Ways how to increase the output power and how to enhance the operation speed are discussed. Because the device is strongly dependent on the coupling between the resonant InP cavity and the silicon waveguide, an extensive analysis of the coupling and the influence of certain process steps on the device performance are given. The PhD thesis concludes the work carried out on InP microdisks and gives an outlook about improving the device performance with respect to specific applications and how to further improve the manufacturability of the devices. Finally, for the InP microdisk-based devices an outlook is given about suitable applications, such as on-chip optical links for instance