Digital PLL for ISM applications

In modern transceivers, a low power PLL is a key block. It is known that with the evolution of technology, lower power and high performance circuitry is a challenging demand. In this thesis, a low power PLL is developed in order not to exceed 2mW of total power consumption. It is composed by small area blocks which is one of the main demands. The blocks that compose the PLL are widely abridged and the final solution is shown, showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz, as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the specifications. The main contributions of this thesis are that this PLL can be applied in ISM applications due to its covering frequency range and low cost 130nm CMOS technology

Low jitter phase-locked loop clock synthesis with wide locking range

The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications systems which employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications applications, but thermal noise induced phase noise have to be minimized in order not to limit their applicability to some applications which impose stringent timing jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL. In this dissertation the fundamental performance limits of CMOS PLL clock synthesizers based on ring oscillator VCOs are investigated. The effect of flicker and thermal noise in MOS transistors on timing jitter and phase noise are explored, with particular emphasis on source coupled NMOS differential delay cells with symmetric load elements. Several new circuit architectures are employed for the charge pump circuit and phase-frequency detector (PFD) to minimize the timing jitter due to the finite dead zone in the PFD and the current mismatch in the charge pump circuit. The selection of the optimum PLL loop bandwidth is critical in determining the phase noise performance at the PLL output. The optimum loop bandwidth and the phase noise performance of the PLL is determined using behavioral simulations. These results are compared with transistor level simulated results and experimental results for the PLL clock synthesizer fabricated in a 0.35 µm CMOS technology with good agreement. To demonstrate the proposed concept, a fully integrated CMOS PLL clock synthesizer utilizing integer-N frequency multiplier technique to synthesize several clock signals in the range of 20-400 MHz with low phase noise was designed. Implemented in a standard 0.35-µm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The specific research contributions of this work include (1) proposing, designing, and implementing a new charge pump circuit architecture that matches current levels and therefore minimizes one source of phase noise due to fluctuations in the control voltage of the VCO, (2) an improved phase-frequency detector architecture which has improved characteristics in lock condition, (3) an improved ring oscillator VCO with excellent thermal noise induced phase noise characteristics, (4) the application of selfbiased techniques together with fixed bias to CMOS low phase noise PLL clock synthesizer for digital video communications ,and (5) an analytical model that describes the phase noise performance of the proposed VCO and PLL clock synthesizer

Signal processing with frequency and phase shift keying modulation in telecommunications

In this paper represents research improving effectiveness of signal processing in telecommunication devices especially for its part, which relates to providing its noise resistance in conditions of noise and interference. This objective has been achieved through development of methods and means for optimization of filtering devices and semigraphical interpretation of clock synchronization systems in telecommunications with frequency shift keying on the base of stochastic models what determines relevance of the subject. Separately, in an article considered the urgent task is using of modified synchronization methods based on the interference influence of adjacent symbols on the phase criterion tract, in particular the use of the modified synchronization scheme, in order to get a formalized outlook representation of the synchronization schemas based on the polyphase structures with using a bank of filters, that allows to improve the characteristics of digital telecommunication channels. This work is devoted to the examination and modeling of these ways. The proposed ideas and results for the construction of synchronization systems can be used in modern means of telecommunication

Editorial: clock/frequency generation circuits and systems

1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2Department of Electronics, University of Pavia, 27100 Pavia, Italy 3Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5Electrical Engineering Department, University of California, Los Angeles, CA 90095, US

An Open-Source LoRa Physical Layer Prototype on GNU Radio

LoRa is the proprietary physical layer (PHY) of LoRaWAN, which is a popular Internet-of-Things (IoT) protocol enabling low-power devices to communicate over long ranges. A number of reverse engineering attempts have been published in the last few years that helped to reveal many of the LoRa PHY details. In this work, we describe our standard compatible LoRa PHY software-defined radio (SDR) prototype based on GNU Radio. We show how this SDR prototype can be used to develop and evaluate receiver algorithms for LoRa. As an example, we describe the sampling time offset and the carrier frequency offset estimation and compensation blocks. We experimentally evaluate the error rate of LoRa, both for the uncoded and the coded cases, to illustrate that our publicly available open-source implementation is a solid basis for further research.Comment: GNU Radio source code available at: https://tcl.epfl.ch/resources-and-sw/lora-phy

Impact and modeling of phase noise in mmW beamforming systems

Abstract. Due to the exponential growth of wireless communication, mobile communication applications require more bandwidth available in higher operating frequencies. High centre frequency makes the systems sensitive for phase variations caused by the phase noise (PN) of the imperfect local oscillators (LOs) used in wireless transceivers. Moreover, wide bandwidth also makes the faster phase variations of the phase noise spectra have an impact on the overall system performance by reducing effective signal-to-noise-ratio. These fast variations seen in the high offset frequencies in the phase noise spectra are typically ignored in the communication systems because the traditional system bandwidths are in order of megahertz, or in maximum few gigahertz. In mmW frequencies, i.e., at 30–300 GHz, the transceivers are typically using multiple antenna elements to achieve the required link range by highly directional beams. Often so-called phased arrays are used to implement the multi-antenna transceiver, where the beamforming is mostly performed in the analog domain by digitally controllable mmW phase shifters. For generating multiple beams from the same transceivers, more than one phased array is typically used in the same platform. The phased arrays often share a single LO, for multiple antenna elements. A typical LO generation architecture is containing a base clock, phased-locked loop (PLL), and some frequency multipliers to achieve the target mmW operating frequency. In multi-array systems, the LO signal can be divided into phased arrays in multiple domains, i.e., the arrays can have an independent clock, and a shared clock, but independent PLLs, shared PLL, or even the final mmW LO can be shared. In different architectures, the phase noise has different behavior, and it can have an impact for example on the beamforming accuracy. This thesis focuses on the effects of phase noise on milimeter-wave (mmW) beamforming systems to study different LO routing architectures. We mainly focus on LO architecture with multiple phased arrays that intend to make a common beamformer and their impact on overall system-level phase noise performance. The specific focus is given to the behavior of the wideband phase noise. The phase noise is modeled by using baseband equivalent models where a gaussian phase noise source is filtered by a filter modeling the equivalent phase noise spectra. The parameterization of the model is based on commercial LO phase noise spectra. The behavior is studied in different LO schemes in single-beam and multi-beam scenarios by using simple examples. The simulations are mostly carried out by using continuous-wave signals, but also the single-carrier modulated QAM waveform is demonstrated. The simulations are performed in MATLAB

Convergence of millimeter-wave and photonic interconnect systems for very-high-throughput digital communication applications

In the past, radio-frequency signals were commonly used for low-speed wireless electronic systems, and optical signals were used for multi-gigabit wired communication systems. However, as the emergence of new millimeter-wave technology introduces multi-gigabit transmission over a wireless radio-frequency channel, the borderline between radio-frequency and optical systems becomes blurred. As a result, there come ample opportunities to design and develop next-generation broadband systems to combine the advantages of these two technologies to overcome inherent limitations of various broadband end-to-end interconnect systems in signal generation, recovery, synchronization, and so on. For the transmission distances of a few centimeters to thousands of kilometers, the convergence of radio-frequency electronics and optics to build radio-over-fiber systems ushers in a new era of research for the upcoming very-high-throughput broadband services. Radio-over-fiber systems are believed to be the most promising solution to the backhaul transmission of the millimeter-wave wireless access networks, especially for the license-free, very-high-throughput 60-GHz band. Adopting radio-over-fiber systems in access or in-building networks can greatly extend the 60-GHz signal reach by using ultra-low loss optical fibers. However, such high frequency is difficult to generate in a straightforward way. In this dissertation, the novel techniques of homodyne and heterodyne optical-carrier suppressions for radio-over-fiber systems are investigated and various system architectures are designed to overcome these limitations of 60-GHz wireless access networks, bringing the popularization of multi-gigabit wireless networks to become closer to the reality. In addition to the advantages for the access networks, extremely high spectral efficiency, which is the most important parameter for long-haul networks, can be achieved by radio-over-fiber signal generation. As a result, the transmission performance of spectrally efficient radio-over-fiber signaling, including orthogonal frequency division multiplexing and orthogonal wavelength division multiplexing, is broadly and deeply investigated. On the other hand, radio-over-fiber is also used for the frequency synchronization that can resolve the performance limitation of wireless interconnect systems. A novel wireless interconnects assisted by radio-over-fiber subsystems is proposed in this dissertation. In conclusion, multiple advantageous facets of radio-over-fiber systems can be found in various levels of end-to-end interconnect systems. The rapid development of radio-over-fiber systems will quickly change the conventional appearance of modern communications.PhDCommittee Chair: Gee-Kung Chang; Committee Member: Bernard Kippelen; Committee Member: Shyh-Chiang Shen; Committee Member: Thomas K. Gaylord; Committee Member: Umakishore Ramachandra

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network