543 research outputs found

    Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

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    Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchersโ€Ÿ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLASโ„ข, a device simulator from SILVACO Inc

    Strain-Engineered MOSFETs

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    This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

    Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

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    This thesis describes a comprehensive, simulation based scaling study โ€“ including device design, performance characterization, and the impact of statistical variability โ€“ on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

    ๋†’์€ ์ „๋ฅ˜ ๊ตฌ๋™๋Šฅ๋ ฅ์„ ๊ฐ€์ง€๋Š” SiGe ๋‚˜๋…ธ์‹œํŠธ ๊ตฌ์กฐ์˜ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ๋ฐ•๋ณ‘๊ตญ.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.์ดˆ๊ณ ๋ฐ€๋„ ์ง‘์ ํšŒ๋กœ ๊ธฐ์ˆ ์˜ ๋ฐœ์ „์€ ๊ณ ์ง‘์ ๋„ ๋‹ฌ์„ฑ์„ ํ†ตํ•ด ๋‹จ์œ„ ์นฉ์˜ ์—ฐ์‚ฐ ์†๋„ ๋ฐ ์šฉ๋Ÿ‰ ํ–ฅ์ƒ์— ๊ธฐ์—ฌํ•  ์†Œํ˜•์˜ ์†Œ์ž๋ฅผ ๋Š์ž„์—†์ด ์š”๊ตฌํ•˜๊ณ  ์žˆ๋‹ค. ํ•˜์ง€๋งŒ ์ตœ์‹ ์˜ ์ƒ๋ณดํ˜• ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด (CMOS) ๊ธฐ์ˆ ์—์„œ ๊ธˆ์†-์‚ฐํ™”๋ง‰-๋ฐ˜๋„์ฒด ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (MOSFET) ์˜ ๋‹จ์ˆœํ•œ ์†Œํ˜•ํ™”๋Š” ๋” ์ด์ƒ ์ง‘์ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ ํ–ฅ์ƒ์„ ๋ณด์žฅํ•ด ์ฃผ์ง€ ๋ชปํ•˜๊ณ  ์žˆ๋‹ค. ํŠนํžˆ ์†Œ์ž์˜ ํฌ๊ธฐ๊ฐ€ ์ค„์–ด๋“œ๋Š” ๋ฐ˜๋ฉด ์ •์  ์ „๋ ฅ ์†Œ๋ชจ๋Ÿ‰์€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ๋‘”ํ™”๋กœ ์ธํ•ด ๊ฐ์†Œ๋˜์ง€ ์•Š๊ณ  ์žˆ๋Š” ์ƒํ™ฉ์ด๋‹ค. MOSFET์˜ ์งง์€ ์ฑ„๋„ ํšจ๊ณผ๋กœ ์ธํ•ด ์ฆ๊ฐ€๋œ ๋ˆ„์„ค ์ „๋ฅ˜๊ฐ€ ์ „์•• ์Šค์ผ€์ผ๋ง์˜ ์–ด๋ ค์›€์„ ์ฃผ๋Š” ๋Œ€ํ‘œ์  ์›์ธ์œผ๋กœ ๊ผฝํžŒ๋‹ค. ์ด๋Ÿฌํ•œ ๊ทผ๋ณธ์ ์ธ MOSFET์˜ ํ•œ๊ณ„๋ฅผ ๊ทน๋ณตํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ์ง€๋‚œ 10์—ฌ๋…„๊ฐ„ ์ƒˆ๋กœ์šด ๋‹จ๊ณ„์˜ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž๋“ค์ด ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๊ทธ ์ค‘ ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ(TFET)์€ ๊ทธ ํŠน์œ ์˜ ์šฐ์ˆ˜ํ•œ ์ „์› ํŠน์„ฑ์œผ๋กœ ๊ฐ๊ด‘๋ฐ›์•„ ์ง‘์ค‘์ ์œผ๋กœ ์—ฐ๊ตฌ๋˜๊ณ  ์žˆ๋‹ค. ๋งŽ์€ ์—ฐ๊ตฌ์—๋„ ๋ถˆ๊ตฌํ•˜๊ณ , TFET์˜ ๋ถ€์กฑํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์€ MOSFET์˜ ๋Œ€์ฒด์žฌ๋กœ ์ž๋ฆฌ๋งค๊น€ํ•˜๋Š” ๋ฐ ๊ฐ€์žฅ ํฐ ๋ฌธ์ œ์ ์ด ๋˜๊ณ  ์žˆ๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์—์„œ๋Š” ์ƒ๊ธฐ๋œ ๋ฌธ์ œ์ ์„ ํ•ด๊ฒฐํ•  ์ˆ˜ ์žˆ๋Š” ์šฐ์ˆ˜ํ•œ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์„ ๊ฐ€์ง„ TFET์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ๋ฐ˜์†ก์ž ์œ ์ž…๊ณผ ๊ฒŒ์ดํŠธ ์ปจํŠธ๋กค์„ ํ–ฅ์ƒ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋Š” ์ˆ˜์ง ์ ์ธต๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„(SiGe) ๋‚˜๋…ธ์‹œํŠธ ์ฑ„๋„์ด ์‚ฌ์šฉ๋˜์—ˆ๋‹ค. ๋˜ํ•œ, ์ œ์•ˆ๋œ TFET์€ CMOS ๊ธฐ๋ฐ˜ ๊ณต์ •์„ ํ™œ์šฉํ•˜์—ฌ MOSFET๊ณผ ํ•จ๊ป˜ ์ œ์ž‘๋˜์—ˆ๋‹ค. ํ…Œํฌ๋†€๋กœ์ง€ ์ปดํ“จํ„ฐ ์ง€์› ์„ค๊ณ„(TCAD) ์‹œ๋ฎฌ๋ ˆ์ด์…˜๊ณผ ์‹ค์ œ ์ธก์ • ๊ฒฐ๊ณผ๋ฅผ ํ™œ์šฉํ•˜์—ฌ ์ œ์•ˆ๋œ ์†Œ์ž์˜ ์šฐ์ˆ˜์„ฑ์„ ๊ฒ€์ฆํ•˜์˜€๋‹ค. ๋‹จ์œ„ CMOS ์†Œ์ž์˜ ๊ด€์ ์—์„œ, ์ „์› ํŠน์„ฑ๊ณผ ์ „๋ฅ˜ ๊ตฌ๋™ ๋Šฅ๋ ฅ์˜ ํ–ฅ์ƒ์„ ์ •๋Ÿ‰์ , ์ •์„ฑ์  ๋ฐฉ๋ฒ•์œผ๋กœ ๋ถ„์„ํ•˜์˜€๋‹ค. ๊ทธ๋ฆฌ๊ณ , ์ œ์ž‘๋œ ์†Œ์ž์˜ ์„ฑ๋Šฅ์„ ๊ธฐ์กด ์ œ์ž‘ ๋ฐ ๋ณด๊ณ ๋œ TFET ๋ฐ ํ•จ๊ป˜ ์ œ์ž‘๋œ MOSSFET๊ณผ ๋น„๊ตํ•˜์˜€๋‹ค. ์ด๋Ÿฌํ•œ ๊ณผ์ •์„ ํ†ตํ•ด, ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ TFET์˜ ํ™œ์šฉ ๊ฐ€๋Šฅ์„ฑ์ด ์ž…์ฆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ๋œ ์‹ค๋ฆฌ์ฝ˜์ €๋งˆ๋Š„ ๋‚˜๋…ธ์‹œํŠธ ์†Œ์ž๋Š” ์ฃผ๋ชฉํ•  ๋งŒํ•œ ์ „์› ํŠน์„ฑ์„ ๊ฐ€์กŒ๊ณ  ์ €์ „์•• ๊ตฌ๋™ ํ™˜๊ฒฝ์—์„œ ํ•œ์ธต ๋” ๋‚ฎ์€ ๋ˆ„์„ค ์ „๋ฅ˜๋ฅผ ๊ฐ€์ง์œผ๋กœ์จ ํ–ฅํ›„ MOSFET์„ ๋Œ€์ฒดํ• ๋งŒํ•œ ์ถฉ๋ถ„ํ•œ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-ฮบ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

    Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

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    With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device

    Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

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    In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate\u27s threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs)

    Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

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    In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs)

    Miniaturized Transistors

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    What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

    Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

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    Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moorรขโ‚ฌโ„ขs Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

    Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

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    Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications
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