Model-Based Design, Analysis, and Implementations for Power and Energy-Efficient Computing Systems

Modern computing systems are becoming increasingly complex. On one end of the spectrum, personal computers now commonly support multiple processing cores, and, on the other end, Internet services routinely employ thousands of servers in distributed locations to provide the desired service to its users. In such complex systems, concerns about energy usage and power consumption are increasingly important. Moreover, growing awareness of environmental issues has added to the overall complexity by introducing new variables to the problem. In this regard, the ability to abstractly focus on the relevant details allows model-based design to help significantly in the analysis and solution of such problems. In this dissertation, we explore and analyze model-based design for energy and power considerations in computing systems. Although the presented techniques are more generally applicable, we focus their application on large-scale Internet services operating in U.S. electricity markets. Internet services are becoming increasingly popular in the ICT ecosystem of today. The physical infrastructure to support such services is commonly based on a group of cooperative data centers (DCs) operating in tandem. These DCs are geographically distributed to provide security and timing guarantees for their customers. To provide services to millions of customers, DCs employ hundreds of thousands of servers. These servers consume a large amount of energy that is traditionally produced by burning coal and employing other environmentally hazardous methods, such as nuclear and gas power generation plants. This large energy consumption results in significant and fast-growing financial and environmental costs. Consequently, for protection of local and global environments, governing bodies around the globe have begun to introduce legislation to encourage energy consumers, especially corporate entities, to increase the share of renewable energy (green energy) in their total energy consumption. However, in U.S. electricity markets, green energy is usually more expensive than energy generated from traditional sources like coal or petroleum. We model the overall problem in three sub-areas and explore different approaches aimed at reducing the environmental foot print and operating costs of multi-site Internet services, while honoring the Quality of Service (QoS) constraints as contracted in service level agreements (SLAs). Firstly, we model the load distribution among member DCs of a multi-site Internet service. The use of green energy is optimized considering different factors such as (a) geographically and temporally variable electricity prices, (b) the multitude of available energy sources to choose from at each DC, (c) the necessity to support more than one SLA, and, (d) the requirements to offer more than one service at each DC. Various approaches are presented for solving this problem and extensive simulations using Google’s setup in North America are used to evaluate the presented approaches. Secondly, we explore the area of shaving the peaks in the energy demand of large electricity consumers, such as DCs by using a battery-based energy storage system. Electrical demand of DCs is typically peaky based on the usage cycle of their customers. Resultant peaks in the electrical demand require development and maintenance of a costlier energy delivery mechanism, and are often met using expensive gas or diesel generators which often have a higher environmental impact. To shave the peak power demand, a battery can be used which is charged during low load and is discharged during the peak loads. Since the batteries are costly, we present a scheme to estimate the size of battery required for any variable electrical load. The electrical load is modeled using the concept of arrival curves from Network Calculus. Our analysis mechanism can help determine the appropriate battery size for a given load arrival curve to reduce the peak. Thirdly, we present techniques to employ intra-DC scheduling to regulate the peak power usage of each DC. The model we develop is equally applicable to an individual server with multi-/many-core chips as well as a complete DC with an intermix of homogeneous and heterogeneous servers. We evaluate these approaches on single-core and multi-core chip processors and present the results. Overall, our work demonstrates the value of model-based design for intelligent load distribution across DCs, storage integration, and per DC optimizations for efficient energy management to reduce operating costs and environmental footprint for multi-site Internet services

ADAPTIVE POWER MANAGEMENT FOR COMPUTERS AND MOBILE DEVICES

Power consumption has become a major concern in the design of computing systems today. High power consumption increases cooling cost, degrades the system reliability and also reduces the battery life in portable devices. Modern computing/communication devices support multiple power modes which enable power and performance tradeoff. Dynamic power management (DPM), dynamic voltage and frequency scaling (DVFS), and dynamic task migration for workload consolidation are system level power reduction techniques widely used during runtime. In the first part of the dissertation, we concentrate on the dynamic power management of the personal computer and server platform where the DPM, DVFS and task migrations techniques are proved to be highly effective. A hierarchical energy management framework is assumed, where task migration is applied at the upper level to improve server utilization and energy efficiency, and DPM/DVFS is applied at the lower level to manage the power mode of individual processor. This work focuses on estimating the performance impact of workload consolidation and searching for optimal DPM/DVFS that adapts to the changing workload. Machine learning based modeling and reinforcement learning based policy optimization techniques are investigated. Mobile computing has been weaved into everyday lives to a great extend in recent years. Compared to traditional personal computer and server environment, the mobile computing environment is obviously more context-rich and the usage of mobile computing device is clearly imprinted with user\u27s personal signature. The ability to learn such signature enables immense potential in workload prediction and energy or battery life management. In the second part of the dissertation, we present two mobile device power management techniques which take advantage of the context-rich characteristics of mobile platform and make adaptive energy management decisions based on different user behavior. We firstly investigate the user battery usage behavior modeling and apply the model directly for battery energy management. The first technique aims at maximizing the quality of service (QoS) while keeping the risk of battery depletion below a given threshold. The second technique is an user-aware streaming strategies for energy efficient smartphone video playback applications (e.g. YouTube) that minimizes the sleep and wake penalty of cellular module and at the same time avoid the energy waste from excessive downloading. Runtime power and thermal management has attracted substantial interests in multi-core distributed embedded systems. Fast performance evaluation is an essential step in the research of distributed power and thermal management. In last part of the dissertation, we present an FPGA based emulator of multi-core distributed embedded system designed to support the research in runtime power/thermal management. Hardware and software supports are provided to carry out basic power/thermal management actions including inter-core or inter-FPGA communications, runtime temperature monitoring and dynamic frequency scaling

SALSA: A Formal Hierarchical Optimization Framework for Smart Grid

The smart grid, by the integration of advanced control and optimization technologies, provides the traditional grid with an indisputable opportunity to deliver and utilize the electricity more efficiently. Building smart grid applications is a challenging task, which requires a formal modeling, integration, and validation framework for various smart grid domains. The design flow of such applications must adapt to the grid requirements and ensure the security of supply and demand. This dissertation, by proposing a formal framework for customers and operations domains in the smart grid, aims at delivering a smooth way for: i) formalizing their interactions and functionalities, ii) upgrading their components independently, and iii) evaluating their performance quantitatively and qualitatively.The framework follows an event-driven demand response program taking no historical data and forecasting service into account. A scalable neighborhood of prosumers (inside the customers domain), which are equipped with smart appliances, photovoltaics, and battery energy storage systems, are considered. They individually schedule their appliances and sell/purchase their surplus/demand to/from the grid with the purposes of maximizing their comfort and profit at each instant of time. To orchestrate such trade relations, a bilateral multi-issue negotiation approach between a virtual power plant (on behalf of prosumers) and an aggregator (inside the operations domain) in a non-cooperative environment is employed. The aggregator, with the objectives of maximizing its profit and minimizing the grid purchase, intends to match prosumers' supply with demand. As a result, this framework particularly addresses the challenges of: i) scalable and hierarchical load demand scheduling, and ii) the match between the large penetration of renewable energy sources being produced and consumed. It is comprised of two generic multi-objective mixed integer nonlinear programming models for prosumers and the aggregator. These models support different scheduling mechanisms and electricity consumption threshold policies.The effectiveness of the framework is evaluated through various case studies based on economic and environmental assessment metrics. An interactive web service for the framework has also been developed and demonstrated

Peak Shaving en Palestina mediante generación fotovoltaica y baterías

En este trabajo se consideran los aspectos técnicos y económicos relacionados con el uso de generación fotovoltaica y baterías en la implementación de estrategias de Peak Shaving en Palestina. El estudio se realiza mediante un proceso de simulación diseñado a tal efecto y que utiliza el perfil de demanda medido en el Hospital Universitario An-Najah, situado en la ciudad de Nablus, y los datos de irradiancia medidos en la estación meteorológica que el Energy Research Center de la Universidad de An-Najah tiene en esta ciudad. Se presentan diversos resultados de simulación que pueden utilizarse a modo de guía práctica para el dimensionamiento energético de estos sistemas y también se ofrecen datos económicos referentes al ahorro económico y plazos de amortización obtenidos.Postprint (published version

Dynamic Processor Reconfiguration for Power, Performance and Reliability Management

Technology advancements allowed more transistors to be packed in a smaller area, while the improved performance helped in achieving higher clock frequencies. This, unfortunately led to a power density problem, forcing processor industry to lower the clock frequency and integrate multiple cores on the same die. Depending on core characteristics, the multiple cores in the die could be symmetric or asymmetric. Asymmetric multi-core processors (AMPs) have been proposed as an alternative to symmetric multi-cores to improve power efficiency. AMPs comprise of cores that implement the same ISA, but differ in performance and power characteristics due to varying sizes of micro-architectural resources. As the computational bottleneck of a workload shifts from one resource to another during its course of execution, reassigning it to another core (where it runs more efficiently), can improve the overall power efficiency. Thus achieving high power efficiency in AMPs requires (i) a diverse set of cores that are optimized for various program phases, (ii) runtime analysis to determine the best core to run on, and (iii) low overhead of re-assigning a thread to a different core type. Decisions to swap threads between AMPs are made at coarse grain granularity of millions of instructions, to mitigate the impact of thread migration overhead. But the computational needs of the program rapidly change during the course of its execution. The best core configuration for an application such that, both power consumption and performance are optimized, changes over time rapidly at fine granularity of thousands of instructions. This dissertation explores ways to design core micro-architecture such that high power efficiency could be achieved, if switching overhead could be lowered, enabling fine grain switching. To take advantage of power saving opportunities at fine grain granularity, this thesis explores reconfigurable/morphable architectures where core resources are reconfigured on demand to suit the needs of the executing application. At first, we explore reconfigurable architectures consisting of two kinds of cores: out-of-order (OOO) big cores and in-order (InO) small cores. The big cores provide higher performance while the small cores are more power efficient. In this proposed architecture, OOO core reconfigures into InO core at run time. Our proposed online management scheme decides to switch between these core types such that we obtain significant power benefits without impacting performance. We also observe that, resource requirements of applications can be quite diverse and consequently, resource bottlenecks or excesses can vary considerably. Thus, reconfiguration between just two core modes may not fully exploit power and performance improvement opportunities. We therefore, explore reconfigurable architectures consisting of diverse core types that not limited to big and little cores. A single core can reconfigure into multiple core modes where each mode has unique power and performance characteristics. Workload performance on a particular core mode depends on a large set of processor resources. Some workloads are highly memory intensive, some exhibit large instruction dependency, some experience high rates of branch mis-prediction, while other workloads exhibit large exploitable instruction level parallelism. A diverse set of core modes is needed, that could address shifting resource needs during various program phases of an application. Different trade-offs in power and performance could be achieved by reducing or expanding the size of various resource. Trade-offs for each core mode are also affected by operating voltage and frequency. We therefore, propose joint core resource resizing with dynamic voltage and frequency scaling (DVFS), which is important for applications whose performance is sensitive to changes in frequency. Thus, at fine granularity, the core should adapt to varying instruction window sizes, execution bandwidth and frequency to meet the demands of the workload at run-time to improve power efficiency. Many current processors employ DVFS aggressively to improve power efficiency and maximize performance. This dissertation studies the tradeoff in power efficiency in using fine grain DVFS and reconfigurable architectures mentioned above.We also explore another important problem due to continued scaling of devices which results in higher vulnerability to soft-errors. We consider dynamic core reconfiguration from the perspectives of both power efficiency and vulnerability to soft-errors. An online management scheme is proposed such that core reconfiguration upon a thread switch not only improves power efficiency but also does not increase the vulnerability to soft errors. In summary, we propose in this thesis several solutions for improving power efficiency by integrating heterogeneity within the core. We also address how popular power reduction techniques like DVFS are comparable to our approach. Finally, we address reliability challenges along with improving power efficiency

Crystal-Less RF Communication Integrated Circuits for Wireless Sensor Networks.

The evolution of computing devices has changed daily life significantly over the past decades, and it is still advancing towards pervasive and ubiquitous networks. At each step, the volume shrinks by 2-3 orders of magnitude while the functionality and computing power remains constant or increases. Wireless sensor networks (WSN) are perceived as the next big step of computing technology for a variety of applications, including environmental sensing, health monitoring, un-obtrusive surveillance and invisible labeling. With thin-film micro-battery technology and CMOS scaling, we can now envision complete sensor nodes with cubic-mm form factors. As node volume reduces, external components like a crystal frequency reference, which does not scale with frequency or process, becomes one of the bottlenecks of realizing cubic-mm WSN node devices. This dissertation covers several aspects of the energy and integration challenges associated with cubic-mm WSN nodes without crystal references. Several new compact and low-power RF circuits for the synchronization and communication of WSN nodes are proposed and discussed. A 60GHz antenna-referenced frequency-locked loop (FLL) using an on-chip patch antenna as both the radiator and the frequency reference has been demonstrated for RF synchronization. The FLL, targeting communication of non-coherent energy detection systems, provides adequate frequency accuracy without crystal references. A 10GHz ultra-wideband (UWB) crystal-less transmitter with an on-chip monopole antenna has also been demonstrated. It operates over the supply voltage range of a micro-battery; generate tunable pulse durations and center frequencies, and lives on an on-chip local decoupling capacitor only. A 1MHz temperature-compensated relaxation oscillator is also proposed in the dissertation for baseband data synchronization. With the modified RC network of the conventional relaxation oscillator, the transfer function of the network has a transmission zero, introducing an additional degree-of-freedom for temperature compensation design. Finally, a 60GHz transmit/receive (T/R) switch-less antenna front-end using an on-chip patch antenna is presented, which has an in-band isolation inherited from the standing wave pattern without implementing a T/R switch. The research projects have explored the circuit design techniques and system integration for cubic-mm energy-constrained devices, achieving both long lifetimes and small volumes for WSN applications.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/99763/1/kkhuang_1.pd

Design of Power Management Integrated Circuits and High-Performance ADCs

A battery-powered system has widely expanded its applications to implantable medical devices (IMDs) and portable electronic devices. Since portable devices or IMDs operate in the energy-constrained environment, their low-power operations in combination with efficiently sourcing energy to them are key problems to extend device life. This research proposes novel circuit techniques for two essential functions of a power receiving unit (PRU) in the energy-constrained environment, which are power management and signal processing. The first part of this dissertation discusses power management integrated circuits for a PRU. From a power management perspective, the most critical two circuit blocks are a front-end rectifier and a battery charger. The front-end CMOS active rectifier converts transmitted AC power into DC power. High power conversion efficiency (PCE) is required to reduce power loss during the power transfer, and high voltage conversion ratio (VCR) is required for the rectifier to enable low-voltage operations. The proposed 13.56-MHz CMOS active rectifier presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration. It is implemented with 5-V devices of a 0.35 µm CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200Ω loading. The linear battery charger stores the converted DC power into a battery. Since even small power saving can be enough to run the low-power PRU, a battery charger with low IvQ is desirable. The presented battery charger is based on a single amplifier for regulation and the charging phase transition from the constant-current (CC) phase to the constant-voltage (CV) phase. The proposed unified amplifier is based on stacked differential pairs which share the bias current. Its current-steering property removes multiple amplifiers for regulation and the CC-CV transition, and achieves high unity-gain loop bandwidth for fast regulation. The charger with the maximum charging current of 25 mA is implemented in 0.35 µm CMOS. A peak charger efficiency of 94% and average charger efficiency of 88% are achieved with an 80-mAh Li-ion polymer battery. The second part of this dissertation focuses on analog-to-digital converters (ADCs). From a signal processing perspective, an ADC is one of the most important circuit blocks in the PRU. Hence, an energy-efficient ADC is essential in the energy-constrained environment. A pipelined successive approximation register (SAR) ADC has good energy efficiency in a design space of moderate-to-high speeds and resolutions. Process-Voltage-Temperature variations of a dynamic amplifier in the pipelined-SAR ADC is a key design issue. This research presents two dynamic amplifier architectures for temperature compensation. One is based on a voltage-to-time converter (VTC) and a time-to-voltage converter (TVC), and the other is based on a temperature-dependent common-mode detector. The former amplifier is adopted in a 13-bit 10-50 MS/s subranging pipelined-SAR ADC fabricated in 0.13-µm CMOS. The ADC can operate under the power supply voltage of 0.8-1.2 V. Figure-of-Merits (FoMs) of 4-11.3 fJ/conversion-step are achieved. The latter amplifier is also implemented in 0.13-µm CMOS, consuming 0.11 mW at 50 MS/s. Its measured gain variation is 2.1% across the temperature range of -20°C to 85 °C

Preliminary design document: Ground based testbed for avionics systems

The design and interface requirements for an avionics Ground Based Test bed (GBT) to support Heavy Lift Cargo Vehicles (HLCV) is presented. It also contains data on the vehicle subsystem configurations that are to be supported during their early, pre-PDR developmental phases. Several emerging technologies are also identified for support. A Preliminary Specification Tree is also presented