Incorporation of feed-network and circuit modeling into the time-domain finite element analysis of antenna arrays and microwave circuits

In this dissertation, accurate and efficient numerical algorithms are developed to incorporate the feed-network and circuit modeling into the time-domain finite element analysis of antenna arrays and microwave circuits. First, simulation of an antenna system requires accurate modeling of interactions between the radiating elements and the associated feeding network. In this work, a feed network is represented in terms of its scattering matrix in a rational function form in the frequency domain that enables its interfacing with the time-domain finite element modeling of the antenna elements through a fast recursive time-convolution algorithm. The exchange of information between the antenna elements and the feed network occurs through the incident and reflected modal voltages/currents at properly defined port interfaces. The proposed numerical scheme allows a full utilization of the advanced antenna simulation techniques, and significantly extends the current antenna modeling capability to the system level. Second, a hybrid field-circuit solver that combines the capabilities of the time-domain finite element method and a lumped circuit analysis is developed for accurate and efficient characterization of complicated microwave circuits that include both distributive and lumped-circuit components. The distributive portion of the device is modeled by the time-domain finite element method to generate a finite element subsystem, while the lumped circuits are analyzed by a SPICE-like circuit solver to generate a circuit subsystem. A global system for both the finite-element and circuit unknowns is established by combining the two subsystems through coupling matrices to model their interactions. For simulations of even more complicated mixed-scale circuit systems that contain pre-characterized blocks of discrete circuit elements, the hybrid field-circuit analysis implemented a systematic and efficient algorithm to incorporate multiport lumped networks in terms of frequency-dependent admittance matrices. Other advanced features in the hybrid field-circuit solver include application of the tree-cotree splitting algorithm and introduction of a flexible time-stepping scheme. Various numerical examples are presented to validate the implementation and demonstrate the accuracy, efficiency, and applications of the proposed numerical algorithms

Taylor-newton homotopy method for computing the depth of flow rate for a channel

Homotopy approximation methods (HAM) can be considered as one of the new methods belong to the general classification of the computational methods which can be used to find the numerical solution of many types of the problems in science and engineering. The general problem relates to the flow and the depth of water in open channels such as rivers and canals is a nonlinear algebraic equation which is known as continuity equation. The solution of this equation is the depth of the water. This paper represents attempt to solve the equation of depth and flow using Newton homotopy based on Taylor series. Numerical example is given to show the effectiveness of the purposed method using MATLAB language

Electric Circuit- and Wiring Harness-Aware Behavioral Simulation of Model-Based E/E-Architectures at System Level

To cope with the rising complexity of automotive electric/electronic architectures (EEA), model-based development at system level is well-established and typically realized in architecture description languages (ADLs) and high-level tools. In this paper, we extend a previously developed approach for automated cross-domain simulation synthesis of model-based EEA descriptions enabling system-level evaluation by a behavioral specification layer. The key contributions of this work are modeling extensions applied to a state-of-the-art EEA ADL to refine specified behavior during synthesis with electric circuits including wiring harness details modeled at the hardware layer. Preliminary experiments show that the novel combination of quantization- and SPICE-based synthesized circuit simulation, conducted in a discrete-event manner and applied to a buck converter, a typical device in an automotive EEA, increases simulation efficiency up to a factor of 2.0 compared to other state-of-the-art tools while preserving accuracy. Finally, another example EEA hardware network, modeling the dynamic current consumption of an Electric Power Steering actuator, applied to a realistic vehicle topology model demonstrates the impact of wiring harness refinements

Formale Verifikationsmethodiken für nichtlineare analoge Schaltungen

The objective of this thesis is to develop new methodologies for formal verification of nonlinear analog circuits. Therefore, new approaches to discrete modeling of analog circuits, specification of analog circuit properties and formal verification algorithms are introduced. Formal approaches to verification of analog circuits are not yet introduced into industrial design flows and still subject to research. Formal verification proves specification conformance for all possible input conditions and all possible internal states of a circuit. Automatically proving that a model of the circuit satisfies a declarative machine-readable property specification is referred to as model checking. Equivalence checking proves the equivalence of two circuit implementations. Starting from the state of the art in modeling analog circuits for simulation-based verification, discrete modeling of analog circuits for state space-based formal verification methodologies is motivated in this thesis. In order to improve the discrete modeling of analog circuits, a new trajectory-directed partitioning algorithm was developed in the scope of this thesis. This new approach determines the partitioning of the state space parallel or orthogonal to the trajectories of the state space dynamics. Therewith, a high accuracy of the successor relation is achieved in combination with a lower number of states necessary for a discrete model of equal accuracy compared to the state-of-the-art hyperbox-approach. The mapping of the partitioning to a discrete analog transition structure (DATS) enables the application of formal verification algorithms. By analyzing digital specification concepts and the existing approaches to analog property specification, the requirements for a new specification language for analog properties have been discussed in this thesis. On the one hand, it shall meet the requirements for formal specification of verification approaches applied to DATS models. On the other hand, the language syntax shall be oriented on natural language phrases. By synthesis of these requirements, the analog specification language (ASL) was developed in the scope of this thesis. The verification algorithms for model checking, that were developed in combination with ASL for application to DATS models generated with the new trajectory-directed approach, offer a significant enhancement compared to the state of the art. In order to prepare a transition of signal-based to state space-based verification methodologies, an approach to transfer transient simulation results from non-formal test bench simulation flows into a partial state space representation in form of a DATS has been developed in the scope of this thesis. As has been demonstrated by examples, the same ASL specification that was developed for formal model checking on complete discrete models could be evaluated without modifications on transient simulation waveforms. An approach to counterexample generation for the formal ASL model checking methodology offers to generate transition sequences from a defined starting state to a specification-violating state for inspection in transient simulation environments. Based on this counterexample generation, a new formal verification methodology using complete state space-covering input stimuli was developed. By conducting a transient simulation with these complete state space-covering input stimuli, the circuit adopts every state and transition that were visited during stimulus generation. An alternative formal verification methodology is given by retransferring the transient simulation responses to a DATS model and by applying the ASL verification algorithms in combination with an ASL property specification. Moreover, the complete state space-covering input stimuli can be applied to develop a formal equivalence checking methodology. Therewith, the equivalence of two implementations can be proven for every inner state of both systems by comparing the transient simulation responses to the complete-coverage stimuli of both circuits. In order to visually inspect the results of the newly introduced verification methodologies, an approach to dynamic state space visualization using multi-parallel particle simulation was developed. Due to the particles being randomly distributed over the complete state space and moving corresponding to the state space dynamics, another perspective to the system's behavior is provided that covers the state space and hence offers formal results. The prototypic implementations of the formal verification methodologies developed in the scope of this thesis have been applied to several example circuits. The acquired results for the new approaches to discrete modeling, specification and verification algorithms all demonstrate the capability of the new verification methodologies to be applied to complex circuit blocks and their properties.Gegenstand dieser Dissertation ist die Entwicklung neuer Methodiken zur formalen Verifikation nichtlinearer analoger elektronischer Schaltungen. Dazu werden im Rahmen dieser Arbeit entstandene neue Ansätze in den Bereichen verifikationsgerechte diskrete Modellierung analoger Schaltungen, Spezifikation analoger Schaltungseigenschaften und formale Verifikationsalgorithmen vorgestellt. Ausgehend vom Stand der Technik der Modellierung analoger Schaltungen für die simulationsbasierte Verifikation wird im Rahmen dieser Arbeit die diskrete Modellierung analoger Schaltungen für zustandsraumbasierte formale Verifikationsverfahren betrachtet. Dazu wurde ein neuer Ansatz zur diskreten Modellierung entwickelt, der die Aufteilungsstruktur anhand der Trajektorien der Vektorfelddynamik bestimmt. So wird eine hohe Genauigkeit der Nachfolgerrelation ermöglicht, woraus eine niedrigere Zahl an Zuständen für ein diskretes Modell gleicher Genauigkeit im Vergleich mit dem bisherigen Stand der Technik folgt. Die Abbildung der Trajektorien-gesteuerten Partitionierung auf eine diskrete analoge Transitionsstruktur (DATS) erlaubt die Anwendung von formalen Verifikationsalgorithmen. Die formale Spezifikation von Eigenschaften in ersten Ansätzen zum Model Checking analoger Schaltungen hat sich stark an den bestehenden temporallogischen Verfahren aus dem Bereich digitaler Hardware orientiert. Ausgehend von einer Analyse digitaler Spezifikationskonzepte und der bestehenden Ansätze für analoge Eigenschaften wurden Anforderungen an eine neue Spezifikationssprache in dieser Arbeit abgeleitet. Die aus diesen Anforderungen im Rahmen dieser Arbeit entwickelte analoge Spezifikationssprache "Analog Specification Language" (ASL) basiert auf einer natürlichsprachlichen Kapselung temporallogischer Operationen, die mit erweiterten Algorithmen zur Transitionspfadbestimmung, Durchführung von Berechnungen auf Zustandsparametern und Oszillationsbestimmung eine hohe Ausdrucksstärke analoger Eigenschaften mit einer anwenderfreundlichen Syntax kombinieren konnte. Die zusammen mit ASL entwickelten Model Checking-Verifikationsalgorithmen zur Auswertung von ASL-Spezifikationen auf einem mit dem Trajektorien-gesteuerten Diskretisierungsverfahren erzeugten DATS-Modell bilden eine wesentliche Erweiterung zum Stand der Technik. Um einen Übergang der Verifikation von signalbasierten zu zustandsraumbasierten Methodiken zu ermöglichen, wurde im Rahmen dieser Arbeit ein Ansatz entwickelt, der die Übertragung von transienten Simulationsergebnissen aus nicht-formalen Testbench-Simulationsumgebungen in eine partielle DATS-Zustandsraumdarstellung ermöglicht. Damit kann, wie anhand von Beispielen gezeigt werden konnte, die gleiche ASL-Spezifikation für Eigenschaften eines vollständigen diskreten Modells ohne Modifikation auch auf Simulationsergebnissen ausgewertet werden. Ein für das formale ASL-basierte Model Checking entwickelter Ansatz zur Erzeugung von Gegenbeispielen für als spezifikationsverletzend identifizierte Zustandsraumgebiete erlaubt es, Transitionsfolgen von einem definierten Startzustand zu einem spezifikationsverletzenden Zustand zu ermitteln. Auf Basis dieses Gegenbeispiel-Verfahrens wurde eine neue formale Eigenschaftsverifikationsmethodik mittels vollständig den Zustandsraum einer Schaltung abdeckenden Eingangsstimuli entwickelt. Die vollständig den Zustandsraum abdeckenden Eingangsstimuli bieten noch eine weitere Anwendungsmöglichkeit im Bereich des Äquivalenzvergleichs. Die im Rahmen dieser Arbeit entwickelte Methodik zum formalen Äquivalenzvergleich auf Basis der vollständig den Zustandsraum abdeckenden Eingangsstimuli ersetzt die anwenderdefinierten Eingangsstimuli durch die vollständig den Zustandsraum abdeckenden. So kann die Äquivalenz für jeden möglichen Zustand der zu vergleichenden Implementierungen anhand eines automatisierten Vergleichs der Simulationsergebnisse beider Implementierungen gezeigt werden. Um die Ergebnisse der neu eingeführten formalen Verifikationsmethodiken visuell zu untersuchen wurde ein Verfahren entwickelt, das den Zustandsraum und seine Dynamik mittels eines Partikel-Simulationsansatzes visualisiert. Da die Partikel über den gesamten Zustandsraum randomisiert verteilt werden und sich dann gemäß der Vektorfelddynamik fortbewegen, kann auch hier ein Einblick in das Systemverhalten gewonnen werden, der eine weitestgehend vollständige und somit formale Repräsentation des Zustandsraums bietet. Die prototypische Implementierung der im Rahmen dieser Arbeit entwickelten formalen Verifikationsmethodiken wurde auf zahlreiche Beispielschaltungen angewendet. Die Ergebnisse für die neuen Ansätze zur diskreten Modellierung, zur Spezifikation und zu Verifikationsalgorithmen analoger Schaltungen zeigen, dass die aus diesen Ansätzen erzeugten Verifikationsmethodiken erfolgreich auf komplexe Zustandsraumstrukturen angewendet werden können

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Efficient computation of partial elements in the full-wave surface-peec method

The partial element equivalent circuit (PEEC) method provides an electromagnetic model of interconnections and packaging structures in terms of standard circuit elements. The surface-based PEEC (S-PEEC) formulation can reduce the number of unknowns compared to the standard volume-based PEEC (V-PEEC) method. This reduction is of particular use in the case of high-speed circuits and high-switching power electronics, where the bandwidth extends from low frequencies to the GHz range. In this article, the S-PEEC formulation is revised and cast in a matrix form. The main novelty is that the interaction integrals involving the curl of the magnetic and electric vector potentials are computed through the Taylor series expansion of the full-wave Green’s function, leading to analytical forms that are rigorously derived. Therefore, the numerical integration is avoided, with a consequent reduction of the computation time. The proposed formulas are studied in terms of the frequency, size of the mesh, and distance between the basis function domains. Three examples are presented, confirming the accuracy of the proposed method compared to the V-PEEC method and surface-based numerical methods from literature

Investigation of surge propagation in transient voltage surge suppressors and experimental verification

An on-going question in the field of surge protection study is how to predict incipient failure of power electronics in the event of a short time, high voltage, and high energy transient surge propagation. The work presented in this thesis addresses the above question by investigating how a high voltage transient surge, whose duration is in the microseconds range, will propagate through the two-level transient voltage suppressor system that is intended to protect sophisticated electronics situated close to the service entrance of a building. In this work the energy patterns relevant to the individual components of the system are evaluated using numerical methods and some of the results are also compared with those obtained using SPICE simulations. Although several mathematical models for surge protection components are discussed in the literature and some device specific ones are provided by manufacturers, there is no evidence to show that a complete analysis, using any such model, has been performed to predict the energy absorptions and associated time lags between the components in a TVSS. Numerical simulation techniques using MATLAB are used to estimate the energy absorption and associated time delays in relation to the propagated transient surge, in individual components of a transient voltage surge suppressor. This study develops mathematical models for particular nonlinear transient surge absorbing elements, specifically for the metal oxide varistor and transient voltage suppressor diode, formulates the state equations which are used to numerically simulate several instances of the transient voltage surge suppressor system, and presents simulation results. All results are validated experimentally using a lightning surge simulator. The outcomes established using the two approaches indicate that the theoretical energy calculations are within 10% of the experimental validations for the metal oxide varistor, which is the main energy absorbing element in the system. The remaining energy distributions in the line-filter components and the transient voltage suppressor diode, which are at least 10 times smaller, are all within 20% of the experimental results. The times at which, the metal oxide varistor and the transient voltage suppressor diode switches to heavy conduction mode are also simulated accurately