Path allocation in a three-stage broadband switch with intermediate channel grouping

A method for path allocation for use with three-stage ATM switches that feature multiple channels between the switch modules in adjacent stages is described. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows path allocation to be performed anew in each time slot. A detailed description of the necessary hardware is presented. This hardware counts the number of cells requesting each output module, allocates a path through the intermediate stage of the switch to each cell, and generates a routing tag for each cell, indicating the path assigned to i

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described

Cell-level path allocation in a three-stage ATM switch

A method of cell-level path allocation for three-stage ATM switches has previously been proposed by the authors. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described. Both uniform and non-uniform models of output loading are considered. The algorithm requires knowledge of the number of cells requesting each output module from a given input module. A fast method for counting the number of requests is described

High-speed cell-level path allocation in a three-stage ATM switch

Path allocation in a three-stage ATM switch is the process whereby bandwidth is reserved through the second stage of the switch for each cell. Cell-level path allocation, performed once in every time slot, ensures that cells are routed through the second stage of the switch without delay or contention. A new algorithm for cell-level path allocation was previously proposed by the author. The motive for supporting intermediate channel grouping in the algorithm is described. The results of the path allocation process must be forwarded to the appropriate cells by a routing tag assignment network. A fast method of routing tag assignment is described, which employs a non-blocking copy network. This reduces the clock rate required of the circuitry, for a given switch siz

Multi-Granular Optical Cross-Connect: Design, Analysis, and Demonstration

A fundamental issue in all-optical switching is to offer efficient and cost-effective transport services for a wide range of bandwidth granularities. This paper presents multi-granular optical cross-connect (MG-OXC) architectures that combine slow (ms regime) and fast (ns regime) switch elements, in order to support optical circuit switching (OCS), optical burst switching (OBS), and even optical packet switching (OPS). The MG-OXC architectures are designed to provide a cost-effective approach, while offering the flexibility and reconfigurability to deal with dynamic requirements of different applications. All proposed MG-OXC designs are analyzed and compared in terms of dimensionality, flexibility/reconfigurability, and scalability. Furthermore, node level simulations are conducted to evaluate the performance of MG-OXCs under different traffic regimes. Finally, the feasibility of the proposed architectures is demonstrated on an application-aware, multi-bit-rate (10 and 40 Gbps), end-to-end OBS testbed

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

by Kin-Yu Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 64-[68]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Multistage Interconnection Architectures --- p.2Chapter 1.2 --- Interconnection Topologies --- p.4Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7Chapter 1.4 --- Organization --- p.8Chapter 1.5 --- Publication --- p.9Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13Chapter 2.1 --- Introduction --- p.13Chapter 2.2 --- Architecture --- p.14Chapter 2.2.1 --- Topology --- p.14Chapter 2.2.2 --- Switch Modules --- p.15Chapter 2.3 --- Routing --- p.17Chapter 2.3.1 --- VP/VC Routing --- p.18Chapter 2.3.2 --- VP/VC Routing Control --- p.22Chapter 2.3.3 --- Cell Routing --- p.23Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24Chapter 2.4 --- SpiderNet --- p.25Chapter 2.5 --- Performance and Discussion --- p.26Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26Chapter 2.5.2 --- Network Capacity --- p.29Chapter 2.6 --- Concluding Remarks --- p.30Chapter 3 --- Multichannel ATM Switching --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Switch Design --- p.40Chapter 3.3 --- Channel Allocation Algorithms --- p.41Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51Chapter 3.4 --- Performance and Discussion --- p.53Chapter 3.5 --- Concluding Remarks --- p.57Chapter 4 --- Conclusion --- p.62Bibliography --- p.6